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path: root/arch/arm/mach-tegra/clock.h
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2013-01-24tegra: apalis_t30: initial Toradex Apalis T30 L4T supportMarcel Ziswiler
Tested on early prototype Apalis T30 V1.0a module. Known issues: - ADC not integrated yet. - HDA not integrated yet. - CEC not integrated yet. - IrDA not integrated yet. - Keys not integrated yet therefore no way to wake from suspend. - 8-bit MMC1 slot card detection interrupt not working despite detection GPIO successfully being tested with GPIOConfig. Note: even 8-bit cards work fine if already plugged-in during boot. - PCIe limited to internal Gigabit Ethernet chip for now due to our proprietary way of resetting other ports which requires further integration into NVIDIA's driver.
2012-11-27tegra: fix file names and paths in commentsMarcel Ziswiler
Several file names and paths showed copy/paste or otherwise issues.
2012-11-12Merge branch 'l4t/l4t-r16-r2' into colibriMarcel Ziswiler
Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
2012-11-02tegra: colibri_t30: hack to avoid lock-up due to missing pll_a lock bitMarcel Ziswiler
At least our early Colibri T30 prototypes exhibit an issue that often times kernel locks-up during boot-up due to missing pll_a lock bit.
2012-08-13tracing: Clock lock trace eventsAntti P Miettinen
Add tracing for clock lock/unlock operations. Bug 960307 Change-Id: Id5c2d8be25900bc701e5dcd73f87c068ab6e5894 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/122666 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-07-30ARM: tegra: clock: increase Tegra3 pll post-lock delaySang-Hun Lee
Bug 1022877 Change-Id: I9200d3345a933ab0ccb31f833184ee4a621228f0 Reviewed-on: http://git-master/r/118774 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
2012-07-23ARM: tegra: clock: Reduce Tegra3 pll post-lock delayAlex Frid
Reduced pll post-lock delay from 50us to 2us. Rearranged wait for lock loop to delay first check of lock bit by 2us after pll is enabled. Added read fence for PLLM lock via PMC (in this case enable bit is in APB bus register, but lock detect bit is in PPSB bus register). Bug 1017271 Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115933 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-13ARM: tegra: clock: Dynamically re-lock memory pllAlex Frid
So far Tegra3 EMC DFS allowed only scaling rates that can be divided down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM is always running at maximum SDRAM rate set at boot time, while PLLP rate 408MHz is fixed across all Tegra3 platforms. This commit implements dynamic re-locking of PLLM at run time. Now memory pll can lock either at boot rate or additional auxiliary rate that is selected as follows: auxiliary PLLM rate must be present in EMC DFS table, it must exactly match one of the rate steps for Tegra3 graphics bus with PLLC clock source (cbus), and must not be a proper factor of boot PLLM rate or PLLP fixed rate. When switching PLLM between boot and auxiliary rate, PLLC is used as backup memory pll, and during this time cbus is locked at auxiliary rate. In addition system bus is forced to temporarily use PLLP as a clock source (this is necessary as sbus main clock source is PLLM secondary divider PLLM_OUT1). Limitations: - only one auxiliary rate is supported, and it should be below PLLM boot rate, but above half of boot rate - dynamic re-lock is allowed only on LPDDR2 platforms - no clock other than EMC and system bus could use PLLM as a source; so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be selected, and VI clock (not covered by PLLM restricted configuration) must be moved to PLLP. Bug 1005576 Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/111438 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a) Reviewed-on: http://git-master/r/114760 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record shared bus backup rateAlex Frid
Added shared bus backup rate entry to clock descriptor; initialized it for cbus (currently the only shared bus with backup source). Bug 1005576 Change-Id: I8124aa87f1dc307e42417da8f78797cfaf71e5dc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110934 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bc5ed688929c3c0ca920b5e9663cf9c6fb85c00f) Reviewed-on: http://git-master/r/114757 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-07ARM: tegra: clock: Add locked version of round rateAlex Frid
Add locked version of round rate API to be used by tegra arch specific layer. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 457627966b91f2141439812869adc4acf9242471) Change-Id: Id68d0bb952d1e7d9e650341872d1b06b0b2d3cea Reviewed-on: http://git-master/r/100474 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-15ARM: tegra: clocks: Consolidate input frequency measurementsScott Williams
Consolidate the functions used to measure the input frequency into a single implementation and perform the measurement only once. Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-03ARM: tegra: clock: Expand PLL usage restriction mechanismVarun Wadekar
Expand PLL usage restriction mechanism from Tegra3 only to common tegra clock framework implementation: fail set parent API if new parent is not allowed per usage policy. Actual usage policy is architecture dependent and exists now only on Tegra3. Reviewed-on: http://git-master/r/77251 Change-Id: I2a8d60cc0ddfd2179961ef50418b193f2e1829c8 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78029 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30ARM: tegra: clock: Update CPU clock scaling dependenciesAlex Frid
Added Tegra3 MSelect clock to memory on CPU clock dependencies: MSelect rate is scaled as half of CPU rate, up to 102MHz. Prevented CPU clock increase if updates of dependent clocks (EMC and MSelect) have failed. Reviewed-on: http://git-master/r/76485 Change-Id: I679b60eb5aa13d5cca2b9751ff2c8c2fb866a076 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77767 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30ARM: tegra: clock: Auto-detect PLLP rate in clock initAlex Frid
Tegra3 platform may boot with one of the predefined fixed PLLP (peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This commit implements auto-detection of PLLP rate, as well as CPU, and system bus PLLP dependencies configuration during clock tree initialization. Bug 928260 Change-Id: I65ea4db2e5cfe96f13566c93e882a3be9deaa129 Reviewed-on: http://git-master/r/75850 Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77295 Reviewed-by: Automatic_Commit_Validation_User
2012-01-16ARM: tegra: clock: Skip clocks in Tegra3 CPU set rateAlex Frid
Reduced Tegra3 CPU clock frequency by skipping every other clock during clock rate change when either old or new rate is above 800MHz. This limits max possible frequency jump when switching between main and back-up clock sources. Added sysfs entry for minimum time to run at reduced frequency (in microseconds): /sys/module/tegra3_clocks/parameters/skipper_delay. Default delay is 10us. It should be adjusted by board initialization code based on board power distribution grid capabilities. Bug 868692 Change-Id: I0c32a3eb91512ba610c4f842bd22ef08e9c889d0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/72682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-on: http://git-master/r/75140 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12ARM: tegra: clock: Split Tegra3 G/LP CPU backup ratesAlex Frid
Separated Tegra3 G and LP CPU backup rates used while main CPU PLL is re-locking. These rates are selected low enough to be safe at minimum voltage, but high enough to avoid voltage droop when CPU clock is switched between backup and main clock sources. Bug 868692 Change-Id: I6b07323a5d3a69d0834b743596aca1e5499781a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/71132 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-on: http://git-master/r/74551 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-01-04tegra3: clock: Support for divisor 15.1Laxman Dewangan
Uart clock source has divisor of 16 bits where LSB is 0.5. Adding support for divisor 15.1 and configuring uart for use the 15.1 type divisor. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: Ifdd77041e7abb43026bbfb273f6e12923d64d607 Reviewed-on: http://git-master/r/70324 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-12-15ARM: tegra: clock: Use Tegra3 PLL lock indicatorsAlex Frid
Bug 873599 Change-Id: Ice84a63d90d39105e53505282fe126e56c4749db Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/68897 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-12-08ARM: tegra: clock: Enforce Tegra3 cbus parent assignmentsAlex Frid
Tegra3 graphics bus (cbus) modules do not use PLLM as a clock source after boot. Explicitly enforced this policy now by failing set parent API if PLLM is selected as a target for any cbus clock. Bug 884419 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit eb2662b7d90af77ee01202e57afa3ed46d4f9053) Change-Id: Ia17972c8c711d3498541ad62aef3961656433665 Reviewed-on: http://git-master/r/67832 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: clock: Update Tegra3 cbus operationsAlex Frid
- Doubled PLLC (cbus parent) rate to make sure that cbus clients always have only even dividers. - Added new shared bus user mode - SHARED_AUTO for user (like Host1x) that just follow the bus, but by itself does not require bus rate above the minimum. Bug 895245 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit e95329c67d4efc424d3408b363e092c02c066ef7) (cherry picked from commit 773e089f2ab676e9ea8afd7aaa0458654a3772d9) Change-Id: Ie1488f38e3cb948d69738c2eef4ae9cd7ae0b47d Reviewed-on: http://git-master/r/67011 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rdd00a21fc2f58efdfeec5733c0307627da1fb430
2011-11-30ARM: tegra: clock: Enable EMC scaling for AP25Prashant Gaikwad
Workaround added to enable EMC scaling for AP25. PLL switching support added for 300MHz EMC scaling step. Bug 892505 Reviewed-on: http://git-master/r/#change,41718 Reviewed-on: http://git-master/r/#change,41720 Reviewed-on: http://git-master/r/#change,60861 Change-Id: I885b8dc4e3b6124ebed572c06cea773de6c83471 Reviewed-on: http://git-master/r/64465 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: Rb8e58cfa7fe1106978030c8aea292e95a7a5da2b
2011-11-30ARM: tegra: clock: Set Tegra3 2D/3D idle divisorsAlex Frid
Enable 2nd level hardware controlled clock gating. (cherry picked from commit 9dc6277e84a504d30dd5c07853301decf66c3060) (cherry picked from commit 0f5ec1901932d78796e143c730ebd9e3f4ffc397) Change-Id: I219a7fcd0e6ee47418cdd444cc101a1c6b266e1f Reviewed-on: http://git-master/r/61706 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R65f5ecab707df40f9e98e954420245c9a4a2c476
2011-11-30ARM: tegra: clock: Use bus lock to protect shared bus updateAlex Frid
Protected shared bus update with bus lock - common for all shared bus users (update procedure was already covered by individual shared users locks, but it did not prevent concurrent access to shared rates list). Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507 Reviewed-on: http://git-master/r/39918 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f
2011-11-30ARM: tegra: clock: Expand Tegra3 shared bus modesAlex Frid
Implemented 3 different modes of combining rate requests from shared bus users : - SHARED_FLOOR: cumulative floor request is determined by maximum rate among all users in this mode and minimum bus rate - SHARED_BW: cumulative bandwidth request is determined by adding rates of all users in this mode together - SHRED_CEILING: cumulative ceiling request is determined by minimum rate among all users in this mode and maximum bus rate Final shared bus rate is determined as minimum rate between cumulative ceiling request and maximum of floor or bandwidth cumulative requests. Up to now shared bus clocks supported only SHARED_FLOOR mode, and this mode is kept as default mode for all users. Hence, no change in actual shared bus operations. Bug 837005 Original-Change-Id: I29f8215ba7bab4998fdd23b74c4f96611f5848fe Reviewed-on: http://git-master/r/39139 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re9f9f87d58419a6756b7985c59743356c6a634bc
2011-11-30ARM: tegra: clock: Add clock rate change notificationAlex Frid
Original-Change-Id: I97434334a4214180a365d9709a331405da135669 Reviewed-on: http://git-master/r/36202 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a
2011-11-30ARM: tegra: clock: Synchronize Tegra3 clocks scalingAlex Frid
On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are sourced from PLLC through integer dividers. Low resolution of these dividers does not allow to set scaling frequency levels matching intermediate voltage steps within core voltage range. Only changing the source frequency can achieve it. However, re-locking common PLL while engines are running requires synchronization of engines clock control, and complex operations including switching to backup sources during PLL stabilization time. This commit introduces a new virtual clock "cbus" to support clocks synchronization and PLLC re-locking procedures. The dvfs table for cbus clock is constructed from frequency steps close to maximum rates for each characterized core voltage level. Engine clocks exposed to the drivers are no longer physical module clocks, but shared cbus users. Setting the rate for such clock specifies the clock floor. The final cbus rate is determined as maximum floor setting for all enabled engines, and rounded up along the cbus dvfs ladder. Actual engine clock rate is set equal to the cbus clock rate. Hence, engines will be running close to maximum frequency for minimum voltage that satisfies all floor requests. Special case: Host1x. This clock will be always configured at 1/2 of cbus clock rate, and its shared user floor request is ignored by cbus target frequency calculations. Added cbus dvfs tables and updated VDE engine dvfs data. Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6 Reviewed-on: http://git-master/r/36199 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915
2011-11-30arm: tegra: clock: Reading APB bus before disabling clockLaxman Dewangan
It may be possible that write operation on apb bus does not get complete before disabling clock if the clock is disabled just after the write on apb bus. To have proper sequence of operation, it is require to read back the apb bus to make sure the write operation is completed. bug 830481 Original-Change-Id: I7f9f68f4cd6d39cf0bd697ddd236c4ce733dcf43 Reviewed-on: http://git-master/r/34413 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R204c12464faad2d3e36fbd1b583e798fab99e248
2011-11-30Revert "arm: tegra: clock: Reading APB bus before disabling clock"Niket Sirsi
This reverts commit 9b2aa51a8b4913948e3061706498c7f91d5aa827. Original-Change-Id: Ie197a9822329c7e36735ef673d0baf69923197de Reviewed-on: http://git-master/r/34389 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R82febd144c3064240a199a67a906b8b481ccd2f1
2011-11-30arm: tegra: clock: Reading APB bus before disabling clockLaxman Dewangan
It may be possible that write operation on apb bus does not get complete before disabling clock if the clock is disabled just after the write on apb bus. To have proper sequence of operation, it is require to read back the apb bus to make sure the write operation is completed. bug 830481 Original-Change-Id: If4767b77a9ac8fdf3253e19d6aebed6c1d13dc5a Reviewed-on: http://git-master/r/32556 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R16af6944cdb3cb87ef6c62fe90dd6481af2a2c2a
2011-11-30ARM: tegra: power: Add suspend index to cpufreq tableAlex Frid
Original-Change-Id: I7bbe018f3786b9683cc9d4189fdcaadb9098f3f1 Reviewed-on: http://git-master/r/31456 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R81da4e2834a9ae209aadba17337d484f26f67ada
2011-11-30ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R30393515042d199154ba708afaefb134402f551a
2011-11-30ARM: tegra: clock: Limit Tegra3 fractional divisors usageAlex Frid
Per Tegra3 characterization results, do not use fractional ratios for dividing host1x/3d/2d/epp/mpe/vi/vde/se clocks. Also prevent using 1:1.5 ratio by system clock dividers (other fractional ratios are still allowed for sclk). Change sclk rounding algorithm to round up divider ladder, since sclk shared bus clock should honor maximum shared user request. Bug 803144 Original-Change-Id: I7b4bb1bb21a4ce4bbfb958c9a603a868dc3c05b4 Reviewed-on: http://git-master/r/29937 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R45798e4d3aff886959c52a9155c257db4c801eda
2011-11-30ARM: tegra: clocks: make pclk div dynamicPrashant Gaikwad
dynamic changing of pclk divider to follow APB clock minimum frequency requirements with respect to sclk frequency. Bug 819796 Original-Change-Id: Id6d4f9321fe3d49922ace9b50cb6e5114f63b9b5 Reviewed-on: http://git-master/r/29643 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb722438f9370900d4536ef9e09a6bcad29521ce0
2011-11-30ARM: tegra: clock: Clip Tegra3 CPU mode rate limitsAlex Frid
Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate are clipped to the entries in cpufreq scaling table. Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07 Reviewed-on: http://git-master/r/29703 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956
2011-11-30ARM: tegra: power: Re-initialize Tegra3 EMC after LP0Alex Frid
Since EMC frequency is not restored after exit from LP0, re-initialize EMC clock with the new warm boot configuration, and make sure that the 1st after LP0 clock change does not use stale timing cache. Skip Tegra2 specific EMC restoration on Tegra3 platforms. Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2 Reviewed-on: http://git-master/r/26807 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406 Rebase-Id: Rb3fcd60c0c674e10d41d4cdc4d8e53a6e124a5bf
2011-11-30ARM: tegra: clock: Add clock time on statisticAlex Frid
Original-Change-Id: I361e00ef84ce4ca9a9c6d7340de2d095fc67a208 Reviewed-on: http://git-master/r/25180 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: If382fc3b5d2ca678df8a9319a06bae967fc3c658 Rebase-Id: Ref4182db3e144202dd2df2047a3683e478e070fc
2011-11-30ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
2011-11-30Update copyrightsScott Williams
Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
2011-11-30ARM: tegra: dvfs: Add Tegra3 EMC and CPU rates dependencyAlex Frid
Original-Change-Id: I28155e59fd6cb36ccd63d8d17ed01b70b9209f97 Original-Change-Id: Ic4ebe6007ab9ee308039ad86c0930f85d116fdd5 Reviewed-on: http://git-master/r/22531 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I4e5e939921d6d82aa8687545399a867901655069 Rebase-Id: R71c8b69183d12414112d88d60fe54a7b85a6d3de
2011-11-30ARM: tegra: dvfs: Add Tegra3 EMC scaling mechanismAlex Frid
Original-Change-Id: I23954a8d005fae93866666fff0e56edb23a49d46 Reviewed-on: http://git-master/r/21940 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I31c3910d38f9999ddbf3414e042e1972d9a86c5a Rebase-Id: Rd6ca05872b34fa23bef682b4185fb4f354632c3a
2011-11-30ARM: tegra: clock: Add DCCON support for Tegra3 PLLMAlex Frid
Original-Change-Id: Ic66ca456e1eef6b3775ca79c23220d1fc436cd76 Reviewed-on: http://git-master/r/17834 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ibd8b119d13d748f186f66947822f6f1b9898f351 Rebase-Id: R33df5ccfd13f0a6b645c7be99fc89e0c8894c5a5
2011-11-30ARM: tegra: clock: Add Tegra3 external output clocksAlex Frid
Original-Change-Id: I2437268b2916d11b1ea9564a06333d8e037a5bc1 Reviewed-on: http://git-master/r/17610 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I49d5248d120233d175a090c27250a32c43ace140 Rebase-Id: R44bdc53347754c7f7e7087883910a779a63410b7
2011-11-30ARM: tegra: clock: Add Tegra3 PLLE supportAlex Frid
Original-Change-Id: Iba29ff515fd850cd0f736d5ef693877e85fb0c5c Reviewed-on: http://git-master/r/16660 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8d6efae37847fcbda12290b6cd5d61e6a61c2777 Rebase-Id: R9a7e6567990346882ad742c43b8ab8f41cfda9d0
2011-11-30ARM: tegra: clock: Add Tegra3 EMC shared busAlex Frid
Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94 Reviewed-on: http://git-master/r/15349 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777 Rebase-Id: R3cab0fa7760e2c6eb5d6e84bbc3dca8f6fe3d3fa
2011-11-30ARM: tegra: clock: Re-factor extended clock operationsAlex Frid
Re-factored extended clock operations to enumerate configuration parameters. Original-Change-Id: I6c1e5f07803a8e6da0ebd6690892f50bb59efcd5 Reviewed-on: http://git-master/r/15144 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I25147998969b385905bad5eb3ceb2dbb89c0d93a Rebase-Id: R815ccca27fac9a0af334c188ce77e0ec4fdad9b2
2011-11-30ARM: tegra: clock: Add extended clock configurationAlex Frid
Some peripheral clock source registers have extra bits with setting specific for the respective controller. Added mechanism to manipulate these bits from the clock code with proper locking. Implemented NAND, VI and DTV extended configurations. Original-Change-Id: Ic8a1887923f0b98f9b1fac06dcf4f90084b017c0 Reviewed-on: http://git-master/r/15059 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Original-Change-Id: Ic3416be8683c90043376d6675269fc23e440f61d Rebase-Id: Rd3e7af5a00bf9580816853456ddb6f19b9bc5b2b
2011-11-30ARM: tegra: clock: Add dynamic UART divider controlAlex Frid
Original-Change-Id: Ie791852555eaae312c1a23f65d68bcb703666368 Reviewed-on: http://git-master/r/14593 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I0568824434b895bcad5691fabbbb12780148e32b Rebase-Id: R38ebb44251dd49e37c280504cf06e84579fb8625
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: clock: Adjust max rates to match SKU IDAlex Frid
Adjust max rates for CPU and several SKU-dependent core clocks (system bus, AVP, VDE, 3D) to match chip SKU ID. Added max_rate node to debugfs. Original-Change-Id: Ifd72d45a303b3d8b5ae5f327693bb97c8510031d Reviewed-on: http://git-master/r/16077 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R7aa44477fd12c9d046baf7ecb8e5e2fcb71818d7
2011-11-30ARM: tegra: cpufreq: Add cpu frequency table selectionAlex Frid
Define cpu frequency tables for different tegra2 CPU clock ranges, and add matching selection mechanism for scaling table as well as throttling limits. Original-Change-Id: I06b13f150d72f8a80f879ecf80ed44cc1f63bad4 Reviewed-on: http://git-master/r/16076 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rc69b8d00284b7bc164d47beb3615b712bfc2c25c
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-13 16:52:49 +0000