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Calculate the tick length of the EMC DFS table
and scale the latency allowance settings.
Bug 955082
Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/124980
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Add a config option to configure early acknowlegement
from memory controller.
Early acknowledgement is feature of memory controller
where MC acknowledged immediately to any write requests
from CPU. To maintain mermory coherency all the read
requests are blocked till all the early-acked writes
have reached to a point of coherency.
bug 943638
Change-Id: I97f30261c4711fc338b007502b6eef7217ddb6cb
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/91477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 935079
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5e70d23ef33dbdf0ce628fd2f287eec1b145dd8e)
Change-Id: Ib8bd72b2cac82b50789f86d034d6ad03b76a657f
Reviewed-on: http://git-master/r/87539
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers
that are not saved in PMC scratch file for boot-rom restoration. Since
SDRAM after LP0 is running at boot rate, MC registers are saved only
once during initialization.
Bug 874351
(ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d)
Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678
Reviewed-on: http://git-master/r/61045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301
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An api (del_timer_sync), which can sleep, should not be used in
hardirq context. This gives warnings for potential deadlock. Use
non-sleeping api to cancel the work instead. In this case, if the
work is already running, it would unthrottle mc error prints.
BUG 889717
Change-Id: I4c0205766d82a45a04d1c0125bb8ed5927757456
Reviewed-on: http://git-master/r/59604
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
Rebase-Id: R713c536217d0169f395ffb199ec2a97b274b9914
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Change-Id: Ic2cecccf0f4f6e6ca612af2ee07acdbca2ce07a5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49281
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R59e04e0a46099403284a036de7f35d21c6188d81
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It's current spot, in tegra_early_init, was too early. It was being
called before we could allocate memory.
Rebase-Id: Rff026504107e75b33dccf714c5219d78c0d1dac9
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Bug 791803
Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432
Reviewed-on: http://git-master/r/23584
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2
Rebase-Id: R3308cf0a852ee2bf0e2adb3de17cebc81e48c71c
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Adding MC_DECERR interrupt handler ported from Froyo.
This addition will not gracefully terminate a failing DMA transfer.
The handler does noting but simply reporting the error status with prink,
and the clinet software will likely hang forever waiting for a non-
completing DMA transfer. But it is still useful for debugging.
Reviewed-on: http://git-master/r/16289
(cherry picked from commit 4c66e8b978f054b332c21a97a53d89f588d24889)
Original-Change-Id: I7b19c70d8cbb62be9ab3f955bf19c707c1e5045d
Reviewed-on: http://git-master/r/16590
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibdcfe63d56d22e39d8c5398ff50eb663bd0d82f3
Rebase-Id: R5a24a2ae2ab4585c3d48c76761beef815a665649
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