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On Tegra3 make sure cpu rate is within G-mode range before LP to G
mode switch triggered by minimum CPUs notifier.
Bug 964208
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99834
(cherry picked from commit 22886da975d44546736b69c64414b56bf3eb7186)
Change-Id: I904cf0155f149977de901ba32f565b496a20f713
Reviewed-on: http://git-master/r/103241
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Boost CPU frequency in tegra platform resume finish phase, just
before driver resume. Boost level is specified by platform suspend
data (ignored if 0).
Bug 946301
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59)
Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e
Reviewed-on: http://git-master/r/89353
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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tegra_throttling_enable function was defined to NULL using a macro
if CONFIG_TEGRA_THERMAL_THROTTLE is not defined.
So replaced the macro definition with dummy inline function for
tegra_throttling_enable function.
Without this change we get "called object '0u' is not a function" error
during compilation.
Bug: 891055
Change-Id: Ie0cb83f0ed43ecf1f21f059dfdeddd56b60f4f0d
Signed-off-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/#change,64129,patchset=2
Reviewed-on: http://git-master/r/67595
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.
- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%
Added tunables:
/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level
Bug 865176
Bug 867186
Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128
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Moved tegra CPU throttling algorithm implementation into a separate
file. For now, the same algorithm is used for both Tegra2 and Tegra3
architecture.
Original-Change-Id: I478c32b5adee4c946472129b89615580c10b41e1
Reviewed-on: http://git-master/r/46748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2340f78e1d22942022e171044d6b20f260e2d312
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Renamed and moved tegra cpu related function prototypes from power.h
to tegra-cpu.h. No functional changes.
Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba
Reviewed-on: http://git-master/r/40532
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3
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The build currently fails for some boards when CONFIG_CPU_FREQ=n, since
we don't build cpu-tegra.c but tegra_throttling_enable is still
referenced. To fix this:
- Add cpu-tegra.h
- Define tegra_throttling_enable to NULL in the header if either
CONFIG_CPU_FREQ or CONFIG_TEGRA_THERMAL_THROTTLE are not set
- Use the header file instead of declaring the function extern
everywhere it's used
Bug 829501
Original-Change-Id: Ice84309546dee201f991a1194fefd80583afc455
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/32208
Reviewed-by: Allen R Martin <amartin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Rebase-Id: Reda9651e2395231d5b1ec7150885d3d9f66ca16b
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