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Renamed and moved tegra cpu related function prototypes from power.h
to tegra-cpu.h. No functional changes.
Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba
Reviewed-on: http://git-master/r/40532
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3
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In K39 , 'freezeable' is changed to 'freezable'.
Reference Commit Id 58a69cb47ec6991bf006a3e5d202e8571b0327a4.
Change-Id: Ie3f95db453205c05da4cf4e655ba8b12a126255b
Reviewed-on: http://git-master/r/47487
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R530643b91e8c252eb606ce7e789cfe34101f6edd
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Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69
Reviewed-on: http://git-master/r/31457
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be
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Made sure Tegra3 LP CPU mode maximum rate, and G CPU mode minimum rate
are clipped to the entries in cpufreq scaling table.
Original-Change-Id: I4c82b65be3a8680edbb501041a7158d1a7fbbd07
Reviewed-on: http://git-master/r/29703
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R99b548e992c80e4850e6d7f9443db8f7d7134956
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When current CPU complex frequency is above target range:
- bring new core on-line only if cpufreq governor requests for
all already on-lined CPUs are above 50% of current CPU frequency
- off-line one core (despite high pick request) if cpufreq
governor requests for at least 2 on-lined CPUs are below 25% of
current CPU frequency
- do nothing if neither of the above conditions is true
Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a
Reviewed-on: http://git-master/r/29702
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9
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- taking CPU core off-line: selected CPU with minimum load
- switching from ULP to G CPU mode: set CPU clock to cpufreq
target rate after the mode switch is completed
Original-Change-Id: I9bf4d0f4b48c262cf678c603aac02043dd602674
Reviewed-on: http://git-master/r/28420
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I5a19be79dd8f8fe788637870a22cd34dcfea150e
Rebase-Id: Re264ec676c5c2103f7738c9eab5f4e11a4344975
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Use cpufreq (cpu DFS) mutex for auto-hotplug (instead of a separate
one) to serialize cpu frequency scaling, hotplug, and CPU mode switch
operations.
Original-Change-Id: I7ea865894d1676c865294ab31a903248d9437534
Reviewed-on: http://git-master/r/24893
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I906a23561c1567079a41590a30b29b3d52fa5de8
Rebase-Id: R5d16154c91b41fd02f2a50af7ec6868a7958dc13
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Added second level virtualization (on top of virtual cpu rate control)
to support different Tegra3 CPU power modes: low power (LP) mode and
geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is
defined as a child with two parents: virtual cpu_lp and virtual cpu_g
clocks for the respective modes. Mode switch sequence was integrated
into cpu_cmplx set parent implementation. (Before this commit mode
switch was triggered outside the clock framework, which created cpu
clock/mode synchronization problems).
Each mode clock is derived from its own super clock mux (cclk_lp and
cclk_g) to statically match Tegra3 h/w layout. (Before this commit the
code had to dynamically synchronize CPU mode and active mux selection).
This change also allowed to support PLLX output divider for low power
mode as fixed 1:2 divider with bypass control embedded into cclk_lp
parent section.
Updated auto and sysfs CPU mode switch calls to use new clock framework,
and removed clock manipulation from the low level mode switch
implementation.
Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b
Reviewed-on: http://git-master/r/24734
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be
Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
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Original-Change-Id: I30e6b308e6c04e4dcb914057284a949ad255d32f
Reviewed-on: http://git-master/r/22708
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I2d221d49aa98d407a18c9d2eb0f5658f56920cbc
Rebase-Id: R84fbe564a1624e2261b4b0623a5fa9d810c1d956
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Do not update auto-hotplug statistic when auto-hotplug is disabled;
initialize and restart updating after it is enabled.
Original-Change-Id: I3a202ab3f0d3d194207e1e881248edac1f820802
Reviewed-on: http://git-master/r/20229
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: Iabc61ecd866b421d7cd819d420051ada83c97b87
Rebase-Id: Rc8e222d920642c2c61587290c8542c69538354a8
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Do not switch to G cluster if cpufreq spikes above LP frequency limit
for a short time - currently set threshold to 100ms. Fixed timing
update for LP cluster statistic.
Original-Change-Id: Id4f00fd5c39d7fe2aa931da30cf607a5144dc3ab
Reviewed-on: http://git-master/r/19381
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: Ief6d391a5806d6cba20b6b5b407acb9846725260
Rebase-Id: Ref560d34203900e32b63d5b6104cb0fb105e4c63
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Forbid cluster switch to G cluster if the G cluster doesn't exist.
Bug 791057
Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23
Reviewed-on: http://git-master/r/19302
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9
Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4
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Add auto-hotplug statistic to track number of transitions and on-line
time for each CPU/cluster.
Original-Change-Id: Iefaf4f69068401eb7a9d4abbf725df4e21d35db9
Reviewed-on: http://git-master/r/19168
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I62209733054dddbc18741b7fca0c481c90f3aba7
Rebase-Id: R3ef66d1e09da307a7aac93082692d8ee27075299
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Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.
When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.
When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.
The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.
Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827
Rebase-Id: R9cf5f5f8868c659db526cb49ddf276a79d93ef1a
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