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path: root/arch/arm/mach-tegra/cpuidle-t2.c
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2012-04-24ARM: tegra2: dvfs: Update DVFS rails statistic for Tegra2Joshua Cha
LP2 state of Tegra2 is considered into rail statistic. Change-Id: Iab2e0fe25ecb8feca1f4aa1040ce5020e6dcf584 Signed-off-by: Joshua Cha <joshuac@nvidia.com> Reviewed-on: http://git-master/r/98118 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-19Revert "ARM: tegra: rethink the cpu suspend-resume code path"Sang-Hun Lee
This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b. Bug 967887 Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96787 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/84481 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-10arm: tegra: REVERT "use unsigned cpuidle latency variables"Joseph Lehrer
Reverting until LP2 hang problem better understood. bug 896827 Reverts I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Change-Id: I9ae1f8e75b77049baf26480691b98e6f9cacca4e (cherry picked from commit c0b30ab66c5f1286a5c1f10777c436a80f8f2fa8) Reviewed-on: http://git-master/r/72905 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com> Tested-by: Joseph Lehrer <jlehrer@nvidia.com> (cherry picked from commit 3d7b52eaf614848e8417c84b819c76faed306503) Reviewed-on: http://git-master/r/73951 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-30arm: tegra: use unsigned cpuidle latency variablesJoseph Lehrer
Latency calculations were using mixed signed/unsigned variables and assignments resulting in very large values which interfered with entering LP2. bug 896827 Change-Id: I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Reviewed-on: http://git-master/r/72151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-12-22ARM: tegra2: power: Fix LP2/LP3 states accountingPrashant Gaikwad
Made sure LP3 state is reported as last entered state to cpuidle governor in case when LP3 is entered as a fall back from LP2 path. bug 905813 Change-Id: I850dddef733d45587875eb796e609b01b1732ab9 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/70012 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2011-12-22ARM: tegra: power: Fix clock event broadcast modePrashant Gaikwad
Do not switch to broadcast mode in common code since it affects both Tegra3 and Tegra2. Tegra3 does not need broadcast mode until final CPU is going in LP2. Bug 905813 Change-Id: I7b888504e5a926c15f34b0bb2487e16f672d9294 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/69686 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-11-30ARM: tegra: power: Fix premature clock event broadcast modeScott Williams
Do not switch to clock event broadcast mode until the final CPU is going into LP2. Switching into broadcast mode on the secondary CPUs can cause double ticking and/or kernel panics on the primary. Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48743 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5
2011-11-30ARM: tegra2: power: fix LP2 statistics reportingJin Qian
Bug 863108 Change-Id: I5cc4e3ba58daeaeb527871026c85bdca5f6362f2 Reviewed-on: http://git-master/r/47232 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R843a5cf74874bad3999bc55caa0eb8cad04cc555
2011-11-30ARM: tegra2: power: Don't disable CPU1 GIC interface in LP2Scott Williams
Leave the GIC processor interface enabled for CPU1 during LP2. Disabling it prevents CPU1 from waking up on IPIs. Change-Id: I32ae01066f21f8b4fba1fd0da392bc691c29bf49 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R16db6ca494653a5d8c61cc7ac2b5cb2c3fa9f46f
2011-11-30ARM: tegra2: power: Fix reset race condition between the CPUsScott Williams
During LP2 for CPU idle on Tegra2, there could be a race condition between the CPUs. CPU1 cannot autonomously shut itself down (put itself into reset). CPU1 must be reset by CPU0 but only when it has no outstanding memory or I/O transactions going on (i.e., it is in the WFI state). CPU1 indicates its readiness to be reset by setting status in a PMC scratch register. If CPU1 wakes up and CPU0 sees CPU1's ready to be reset status before CPU1 can clear it CPU1 could be reset at inappropriate times resulting in loss of cache coherency and ultimately a kernel panic. Eliminate the race condition by ensuring that: - CPU1's reset ready status is cleared as early as possible before CPU1 rejoins the coherent world. - Use writel when updating the IRAM LP2 status flags to ensure the IRAM and coherent memory views of the flags are consistent. - If there is not enough time remaining for CPU1 to be in LP2 for the minimum residency time, clear CPU1's reset status flag before entering WFI so that CPU0 will not wait for CPU1 to be ready to reset (since it won't be if there is insufficient time). Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848
2011-11-30ARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculationScott Williams
CPU 0 must wake up before CPU 1 therefore CPU 0 must be awake by the minimum of its or CPU 1's absolute wakeup time. However, the the CPU idle request time is a duration not an absolute time. Change the LP2 sleep time calculation to use an absolute "must be away by" time. Change-Id: Ia73dcbe071f81d0bd9fc6c5d860837e606575a8c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R138e6d4ae652932607f7dd411be3aa89ee53e34c
2011-11-30ARM: tegra: power: Fix Tegra2 LP2 modeScott Williams
All CPUs are not created equal. CPU0 must be the one to perform the CPU complex suspend actions. CPU complex power gating and rail gating cannot be triggered from CPU1. The Linux 2.6.39 port for Tegra2 violates this hardware restriction. While it may have appeared that the system was entering LP2 state, when entered on CPU1, essentially all that happened was a WFI with no CPU complex power gating and no CPU rail gating. Change-Id: Ie754520264fe8de1b95f523d6575914bf77e747f Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R66e19457bc55bcd84124e3a4e23beae7b4ee707c
2011-11-30ARM: tegra: Add Tegra GIC extensionsScott Williams
Implement extensions to the standard ARM GIC API for Tegra3 power management. Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: LP2: Update statisticsScott Williams
Change-Id: Ic878edc316865df79a571255fd0462360599472a Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R206b2c1cd07c360ea2f5be1a54c9b29944bc1df3
2011-11-30ARM: tegra: LP2: Choose the earliest wakeup requestScott Williams
This will wake up earlier if the other CPU's request is shorter. Change-Id: I0abf20d482e5bd28893b2e014fcf50e6ac557241 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R65c18d77baf7b49be32bb7eb6825af2d1865d356
2011-11-30ARM: tegra: Add LP2 exit latency correctionScott Williams
Change-Id: I37cb57f8674d8ddea3861fdc59543c3dfa8498db Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0a1d0c79e22f9191bde70b8b05541c5bfe26f4df
2011-11-30ARM: tegra: Keep track of actual LP2 timeScott Williams
Change-Id: I570b771b67f76123fb81b41ceb27bebb9c9e011f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5cace01cb03450d21fda2aca33ea806f13cc3015
2011-11-30ARM: tegra: Catch early LP2 exitsScott Williams
Change-Id: I107d301ec8e8cd3b69ea293faab15b8d766e38f4 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9f8f016c1850e2c65f30f2f67241a94acf8a7755
2011-11-30ARM: tegra: Prevent LP2 if request is less than target residencyScott Williams
Change-Id: Icc7409b611439ba94ec504579c00ab9227c9a857 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R4b56e98c821627de480a67c241363608ebfc2f07
2011-11-30ARM: tegra: Idle event wakeup timerScott Williams
Change-Id: If072ef10f02d5be7560fdf42584ab11b2a863481 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1ace67e281b1581501aaa936cd9137d326f2c4a
2011-11-30ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
2011-11-30ARM: tegra2: Move LP2 into cpuidle-t2.cScott Williams
Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624
2011-11-30ARM: tegra: Move Tegra2 idlestats to cpuidle-t2.cScott Williams
Change-Id: I2c0814cfefd820626beeba468edd9c462c6be8bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbb70f49af4e731c953315ae81a96480ac25ff4d
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