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2012-08-21ARM: tegra: Remove timer workaroundAntti P Miettinen
Reprogramming running timers may cause timer interrupt state to get out of sync and result in lost timer interrupts. Bug 950482 Change-Id: I83c9d735f9b041e8a57d73ba466f5f9c89ca1b89 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/111242 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-08-15ARM: tegra: power: Trace LP2 entry and exitAntti P Miettinen
Add traces for measuring LP2 entry/exit times. Bug 960304 Change-Id: I20bb0f8d55a7ed6f7e88e10d924871a3d09f2507 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/123313 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-02-03ARM: tegra: power: Separate lp2 latency for G/LP CPU modesAlex Frid
Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes. Separately measure and adjust latency in each mode; restart calculation after mode switch from the last measured latency in the target mode. Reviewed-on: http://git-master/r/78344 Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78902 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-03ARM: tegra: power: Report LP3 state if LP2 is not allowedAlex Frid
Properly report LP3 state to idle governor when LP2 entry is not allowed and LP2 request is redirected to LP3. Reviewed-on: http://git-master/r/77956 Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78697 Reviewed-by: Automatic_Commit_Validation_User
2012-01-10arm: tegra: REVERT "use unsigned cpuidle latency variables"Joseph Lehrer
Reverting until LP2 hang problem better understood. bug 896827 Reverts I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Change-Id: I9ae1f8e75b77049baf26480691b98e6f9cacca4e (cherry picked from commit c0b30ab66c5f1286a5c1f10777c436a80f8f2fa8) Reviewed-on: http://git-master/r/72905 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com> Tested-by: Joseph Lehrer <jlehrer@nvidia.com> (cherry picked from commit 3d7b52eaf614848e8417c84b819c76faed306503) Reviewed-on: http://git-master/r/73951 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-30arm: tegra: use unsigned cpuidle latency variablesJoseph Lehrer
Latency calculations were using mixed signed/unsigned variables and assignments resulting in very large values which interfered with entering LP2. bug 896827 Change-Id: I8c8226433d26efbbc1579372c9a73cbc5897f26c Signed-off-by: Joseph Lehrer <jlehrer@nvidia.com> Reviewed-on: http://git-master/r/72151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-12-22ARM: tegra: power: Fix clock event broadcast modePrashant Gaikwad
Do not switch to broadcast mode in common code since it affects both Tegra3 and Tegra2. Tegra3 does not need broadcast mode until final CPU is going in LP2. Bug 905813 Change-Id: I7b888504e5a926c15f34b0bb2487e16f672d9294 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/69686 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-12-15Revert "ARM: tegra: power: Use peek ahead timers not event notification"Prashant Gaikwad
This reverts commit 3f5e640849383b1d5ed551aa84e0a89578519f09. Change-Id: I5af3fab193204d121a0ea4a939d6e950d2c4a633 Reviewed-on: http://git-master/r/68680 Reviewed-by: Andy Park <andyp@nvidia.com> Tested-by: Andy Park <andyp@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-11-30ARM: tegra: power: Fix LP2/LP3 states accounting on Tegra3Alex Frid
- Made sure LP3 state is reported as last entered state to cpuidle governor in case when LP3 is entered as a fall back from LP2 path. - Accumulate idle time designated to LP2 state by cpuidle governor and time actually spent in LP2 by each CPU separately. Update LP2 statistic output. Change-Id: I55b461e94925ba7a41112756ed958f81fc0bc882 Reviewed-on: http://git-master/r/60381 Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R240873bd1de225696d392ac5ba2c3d517c59d86e
2011-11-30ARM: tegra: power: Update Tegra3 LP2 time predictionAlex Frid
Use local timer count to predict time to be spent by secondary CPU in LP2 state instead of scheduler timing. This is more accurate, as local timer wakes CPU after counts down to zero. Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35 Reviewed-on: http://git-master/r/55629 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631
2011-11-30ARM: tegra: power: Initialize and update LP2 exit latencyAlex Frid
Change-Id: Id6bacc252774758d9ea03b7f2cc91897b5817e10 Reviewed-on: http://git-master/r/55069 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Ra8e8dfed500041886700a8fd44b0b917367225b3
2011-11-30arm: tegra: Disable LP2 mode by default.Krishna Reddy
LP2 should be enabled through board specific init rc file. Change-Id: I2772ad0ccd04fd3933a2286c6335304d2bef60cd Reviewed-on: http://git-master/r/53920 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Ra46b97752305db9e3ac2400162872c5e5863034e
2011-11-30ARM: tegra: power: Fix premature clock event broadcast modeScott Williams
Do not switch to clock event broadcast mode until the final CPU is going into LP2. Switching into broadcast mode on the secondary CPUs can cause double ticking and/or kernel panics on the primary. Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48743 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5
2011-11-30ARM: tegra: power: trace C states and CPU mode switchesPeter De Schrijver
Original-Change-Id: I7915d356f18ac830c93b736463406b907d8c1cef Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31958 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R341f7619d11f81fd7dfbab2ceb1c6fdaab6ead78
2011-11-30ARM: tegra: power: Reorganize CPU idle codeScott Williams
Change-Id: I57653997b7dc059f74e0722b9ea298f3d8a38095 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc8638db0a47faf6fe25976375542fb6eb6326c4c
2011-11-30ARM: tegra: power: Save TWD registers on cluster transitionsScott Williams
The ARM timer/watchdog (TWD) registers do not need saving on LP2 transitions resulting from real idle events. They do still need saving/restoring on transitions resulting from cluster control operations. Change-Id: I459b25b98c256a52a2e9e68fb63dbf2681e90b07 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R3c7c0cae8b847af6355fa1fa0b8bf5bf1e1efef5
2011-11-30ARM: tegra: power: Disallow LP2 in idle if permanently disabledScott Williams
For a variety of reasons, it is possible that LP2 in idle can never be allowed. If one of these conditions exists, do not allow LP2 in idle to be re-enabled via the module_param interface. Change-Id: I980f147844ad9374c218bfb2a25c0d91dad85281 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb897f6dc8245e525fd9ac90c9243e290307c4e58
2011-11-30ARM: tegra: LP2: Update statisticsScott Williams
Change-Id: Ic878edc316865df79a571255fd0462360599472a Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R206b2c1cd07c360ea2f5be1a54c9b29944bc1df3
2011-11-30ARM: tegra: Add LP2 exit latency correctionScott Williams
Change-Id: I37cb57f8674d8ddea3861fdc59543c3dfa8498db Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0a1d0c79e22f9191bde70b8b05541c5bfe26f4df
2011-11-30ARM: tegra: Prevent LP2 if request is less than target residencyScott Williams
Change-Id: Icc7409b611439ba94ec504579c00ab9227c9a857 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R4b56e98c821627de480a67c241363608ebfc2f07
2011-11-30ARM: tegra: Make LP2 require CONFIG_PM_SLEEPScott Williams
Change-Id: Iaaf96375eaf7408f5bedc4196d33a04fb94129ef Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R98567e0d894acbdac770b191f7e46f16592d5d0b
2011-11-30ARM: tegra2: Move LP2 into cpuidle-t2.cScott Williams
Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624
2011-11-30ARM: tegra: Move Tegra2 idlestats to cpuidle-t2.cScott Williams
Change-Id: I2c0814cfefd820626beeba468edd9c462c6be8bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbb70f49af4e731c953315ae81a96480ac25ff4d
2011-11-30ARM: tegra: Add cpuidle.hScott Williams
Change-Id: I75ec091f9dcd0fa3fa56b1542f58a02006c1a314 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ree5fce2632aff6dc59879817ad7ad3f2b1538244
2011-11-30ARM: tegra: power: Restore LP2 in idle protectionsScott Williams
Restore the code that was dropped in the port to Linux 2.6.39 that protects against using LP2 mode for idle when the platform suspend mode has disallowed the use of LP2 mode. Also cleans up some warning messages. Change-Id: I357210b8a272c10bf7c1e773342dc864bbddb74e Reviewed-on: http://git-master/r/40463 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6a60e3f0f2ebf06ec9701475af41679c24ef80ab
2011-11-30ARM: tegra: power: Restore tegra_cpuidle_pm_notifier registrationScott Williams
Restore the registration of the CPU idle power management notifier callback that was removed when porting to Linux 2.6.39. There is no reason why individual CPUs should be trying to go into the LP2 state when the system is suspending. Change-Id: I227948a60fa958b464ceb889d3369fbba2e8c8fd Reviewed-on: http://git-master/r/40462 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R27753c83d40b0407204090e94e6948cdc6449e5b
2011-11-30ARM: tegra: power: Set minimum LP2 target residencyAlex Frid
Added board level tuning parameter to specify minimum LP2 residency time (previous policy allows down to zero residency targets limited only by LP2 exit latency). Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22 Reviewed-on: http://git-master/r/28162 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Original-Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6 Rebase-Id: Rcf9efce3dd037b0a7ca13a9c342f884fac38d654
2011-11-30ARM: tegra: power: Use peek ahead timers not event notificationScott Williams
Use peek ahead timers instead of clock event notification for CPU idle. Original-Change-Id: I14942ab51920f59e0dc0d4892ec2c32e073d2146 Reviewed-on: http://git-master/r/24515 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I4c781b328a2a8b9fa5ac8fa28970e03d3cadafa2 Rebase-Id: R894866485f818aad0ae776c474530e8be5969d32
2011-11-30arm: tegra: Do not write read-only bitsScott Williams
AXI_FLUSH_DONE (bit 31) of CLK_RESET_CLK_MASK_ARM is a read-only status bit. Do not write it. Reviewed-on: http://git-master/r/16456 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> (cherry picked from commit 34add7dc2e7398763fe36db7f4e79657cdd6e95e) Original-Change-Id: Ia480e1b3113f7690ce6431f337b0c9354566d2ef Reviewed-on: http://git-master/r/16936 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ic3ae3fa92e563f27a7b0bf5fe1d4c14a9d953ed6 Rebase-Id: R2405ee8d5543270fc4e103a8c53d9b6c6e1809aa
2011-11-30PARTIAL arm: tegra3: Add CPU idle supportScott Williams
Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063 Reviewed-on: http://git-master/r/14167 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6 Rebase-Id: Rb3ac2fff9435330ec65c5541d369b743c9cb898f
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: cpuidle: Remove fiq enable/disableColin Cross
Change-Id: I52881da51ba1daf95a960c8fc834dd2f1be824c4 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: tegra: Handle timers during LP2 idle ticksTodd Poynor
Timer ticks aren't properly serviced while a CPU is in LP2 idle. Although the Tegra LP2 idle code calls hrtimer_peek_ahead_timers, because no IRQ regs have been saved, update_process_times is not called, and thus the timer list is not serviced (and neither is SMP rebalancing, etc.) This can cause significant delays scheduling timer-based activity, especially on CPU 1 (which is not servicing most other IRQs). Colin Cross suggested a patch based on upstream review feedback that uses clock notifiers to switch to the "broadcast" clock event source ("timer0" Tegra timer 3) during LP2, which has a real interrupt handler defined that calls the clock event handler in IRQ context, allowing timers to be checked. Change-Id: Ifa3f4ec662f07dc9636e433f278358f75b65d10c Signed-off-by: Todd Poynor <toddpoynor@google.com>
2011-11-30ARM: tegra: add cpuidle driverColin Cross
Supports clock-gated (LP3) SMP idle mode, and power-gated (LP2) idle. Latency for LP2 idle state is calculated as a 2-sample weighted moving average, to allow for variations due to CPU frequency scaling. LP3 idle gates a single CPU core, but LP2 requires power gating both CPU cores. When the first CPU requests to enter LP2, it saves its own state and then enters WFI. When the second CPU requests LP2, it attempts to put the first CPU into reset to prevent it from waking up, with some synchronization in case it was already awake, and then powers down both CPUs together. Change-Id: I1dc2a7fb9b3bff524952d0cbf3c322a7b9a38be9 Signed-off-by: Colin Cross <ccross@android.com>
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