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If there are no callbacks associated with the request,
dma interrupt is not enabled.
Bug 969125
Change-Id: Ifbf2a8d6c474187927ee38af03cb96e53e199b83
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/96724
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Added tegra_dma_get_channel_id API to determine the id
of a given channel.
Bug 969125
Change-Id: Ibad67d65c87dc267a4e6942557c02acbd0f6e938
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/96714
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
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When canceling dma, updating actual bytes transferred by dma,
making all requests status to aborted and deleting from channel
request queue.
Change-Id: I860780814340d54465de5b2ae11a6895319f428c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90815
Reviewed-by: Automatic_Commit_Validation_User
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Adding new req status TEGRA_DMA_REQ_PENDING. This will be initial
status of the request when enqueued.
Change-Id: I67ee71dd0c64b6398305b86fbf186488f062e876
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/93801
Reviewed-by: Automatic_Commit_Validation_User
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The dma will be stop in continuous mode with following reason:
- There is no next request and dma restarted the same buffer
as it was last transfer.
- The buffer size was not enough and so latency to serve dma interrupt
is more than buffer transfer time and hence buffer completed before
interrupt served.
In the above cases, dma actually transfer more than requested
size. Returning correct transferred data in byte transferred and
return request status as ERROR.
Change-Id: I7046e0935b7261475a0f6ed49e40a6f1b86d72ec
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86002
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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The request size should be multiple of 4 bytes in ONE_SHOT and
CONTINUOUS_SINGLE mode and multiple of 8 bytes in case of
CONTINUOUS_DOUBLE mode.
Change-Id: Iedb7a75eedda58f4f9b5c6d072ef2edb7ee657d4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87994
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Some cleanups:
- Copyright year change
- Properly aligned macro.
- Defined function as static if used only in file.
- Move the macro from header to file if it is only used in driver.
- Returning proper status on callbacks.
- Adding some more comments in code.
- Rewritten some piece of code for better readability.
Change-Id: I778752668a67b849859fd7e0c11f2b7a3f3b1edc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87993
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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When doing the cleanups in isr, the request was deleted
two times after full buffer completion on double buffering
of dma mode.
Removing extra request deletion.
Change-Id: I6ef30b67d5d73bbc1d7a479d75b8e6ccba6a6f0a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87992
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Disabling clock of apb dma in suspend and enabling back on
resume.
Change-Id: I6320072ea25565bcab4833c9b10dcb6a9d526ac6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87991
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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The clock name is "tegra_dma" for getting proper clock structure
and using this for resetting dma.
Change-Id: I44819ccc25d42f15b14a42d6616c776fa1ad95ec
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87990
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Initialize the interrupt handler of dma channel when it is
allocated.
De-initialize when the allocated channel get free.
Change-Id: Ic813cb28492cc26907d0fcfdf573600a586d1c63
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/87231
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Use the helper function for starting head request from
queue/configuring the next request from transfer in place
of doing it in multiple places. This removes the duplicating
of code in multiple places.
Change-Id: I273f6666a1cd2debcdab56593aa9bf0e9c50318d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86914
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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In order to avoid the passing of the spin lock irq flags
to different isr handler, calling the callbacks from main
isr itself. Callback function should be call without spin
lock.
Change-Id: I9e9980cef5d1de4dd4e31b8ef5fdff223b77bb22
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86873
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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Define the global address as static global in file and
uses this in different functions. This way, it will avoid
the same definition at multiple functions.
Change-Id: I71d7ec075c70356c52ae9ce36339b4b9cc082f70
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/86872
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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The apb dma supports next transfer configuration before current
on-going transfer completes in continuous mode.
The new configuration require multiple register programming and need
to be done before last burst completed. Just after last transfer
completes, the new configure data is reloaded.
To make this configuration atomic, pausing the dma during configuration
so that last burst should not be happen and dma engine should not re-load
new configuration when it was on a way.
bug 937142
Change-Id: I15b62394df10c97ca21c0d7905fedc7e7c2872b7
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/84292
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
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In order to get the correct the transferred count done by dma,
use the requested size from client request instead of transfer
count programmed on dma.
Change-Id: I6d78b0435820ecb1db4b2de2569a2f9d728b2d05
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77795
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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The dma interrupt status should be cleared with spin lock held
to provide the proper synchronization between get_channel_status()
and dma isr.
The interrupt status flag is used to get the transferred data
done by dma and hence the status check and transfer count update
should be atomic.
Change-Id: I9c60f818e95eb32b362abea1afe19c92a23e6827
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/79191
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Fixed the checkpatch error and doing code cleanups.
Change-Id: Ice966d80e4b7175b72ce218197f6ff5ebd7d8c67
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/79404
Reviewed-by: Automatic_Commit_Validation_User
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The functon tegra_dma_dequeue() duplicates the functionality
of tegra_dma_dequeue_req().And this function does not use proper
locking before accessing the channel data.
Removing this function.
Change-Id: Ib6baaa984b038908c49adb3a0f3df3433f0a9066
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77805
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Dma user must call the function tegra_dma_get_transfer_count()
for knowing transferred count without stopping dma.
Change-Id: I5e0060fd8163b285496442268548a90bdd0e294c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/77800
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
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Since dtv interface was designed based on SPI bus, it shares the same
dma configuration with SPI bus. However, it is not proper because DTV
interface has to transmit data in 4 words long constantly. The patch
added an option in tegra_dma_req to set burst size to be fixed 4 words.
fixed Bug 910227
Change-Id: I1436f0c8d108dd39edc57ae4c9cb750d9574b62c
Reviewed-on: http://git-master/r/75509
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76461
Reviewed-by: Automatic_Commit_Validation_User
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- add missing error code
- remove duplicate define
Bug 919369
Bug 919338
Change-Id: I03012050f3b6c4b7bda69657fdd5cb533dcd937e
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/74521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/75544
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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Added EXPORT_SYMBOL to functions to be used by loadable kernel module
for audio test framework. Also added ioctl declarations for the same.
Change-Id: Id8a023c1d76fd031c042c7c663bb0e1df2d33b5c
Reviewed-on: http://git-master/r/52333
Tested-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: Rfdc9fd3b9a42b2ee601c273480f9986ab897f046
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For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration
parameter to use on Tegra for power management, and not CONFIG_PM.
CONFIG_PM does not have the required dependency on CONFIG_SUSPEND
necessary to pull in the CPU suspend/resume functionality used by
Tegra.
Also fixes compilation errors when CONFIG_PM and by implication
CONFIG_PM_SLEEP are not configured.
Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad
Reviewed-on: http://git-master/r/40458
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
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Change SOC conditionals to make them more forward-looking.
Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998
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Adding the debug fs interface to watch the dma registers
from user space.
Original-Change-Id: I42204b0fdd2aa201006c4cc96d2448aa24b98fc5
Reviewed-on: http://git-master/r/29624
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R824c47307c3fa8ae01e29def4fca3924a6815c5b
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By changing the dma allocation API to take the client name, it is easy
to track who is allocated the DMA channels when we run out of the
DMA channels.
Original-Change-Id: I016011cfd74089fed0da1bc0f121800017ce124a
Reviewed-on: http://git-master/r/28031
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Original-Change-Id: I048bcb87f95ee6d8ad2fdce993a1758dc5071666
Rebase-Id: R08ce682381dad3170a335f47333f0a6afb8d4579
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Resetting the apb dma controller and enabling the clock of the
apb dma controller during kernel initialization.
Making necessarily entry for the apb dma clock in clock table.
Original-Change-Id: Ifaed5a70ed06b162a5015a2eae8bb444b43178c4
Reviewed-on: http://git-master/r/27873
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Original-Change-Id: If66c96a5e9cd015086f4d407ed9fc9bd99b6b29f
Rebase-Id: R7a8cd4e1f6e3df6bed0f3dbc105bb2c349f9a6cc
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Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a
Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
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Setting burst size of dma based on the transfer size for the
client i2s for tegra3 architecture.
Setting burst to 4 word for tegra2 architecture.
bug 796817
Original-Change-Id: I6c9e4ab775fb23d51207084b231745fc7a4f60d8
Reviewed-on: http://git-master/r/21102
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: Ib5c639bb33d2a05060ff62bc75a2e43f655310f9
Rebase-Id: R9c6e81845fbaf3f25f395500e307474d0885bce2
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Original-Change-Id: Ia098e22789f4817e14ac34de01f8d990b4b4d29b
Reviewed-on: http://git-master/r/15975
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If9677ac2190d8d2266ee40d011f5841e97838522
Rebase-Id: R2a64c748b9d73d8c833ef09aa3c7d19b7eee532b
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Conflicts:
arch/arm/configs/tegra_defconfig
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-ventana-power.c
arch/arm/mach-tegra/board-ventana-sensors.c
arch/arm/mach-tegra/board-ventana.c
arch/arm/mach-tegra/clock.c
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/cpu-tegra.c
arch/arm/mach-tegra/fuse.c
arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/tegra2_dvfs.c
arch/arm/tools/mach-types
drivers/rtc/rtc-tegra.c
drivers/usb/gadget/fsl_udc_core.c
drivers/video/tegra/host/dev.c
drivers/video/tegra/host/nvhost_channel.c
drivers/video/tegra/host/nvhost_intr.c
Original-Change-Id: I1e9b6d0e761cf1e95cf90b78b5932b53fcb9bb5e
(cherry picked from commit 2f331e046f7c4cfc6ab54fca3193035b3bf3a14f)
Reviewed-on: http://git-master/r/14572
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I29db8796b2e27a8d218c332de36f880a7cf4bcb2
Rebase-Id: R54dfb0d8e2534ea0c13c1157933d30a4198acbbf
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Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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Adding api for getting the amount of data trsnaferred by dma.
Original-Change-Id: I348b8a2f0f855165fb1bf74f0d9013faa97056e7
Reviewed-on: http://git-master/r/20377
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Raf91b00545ff2e61f14c7136972d807c6afb96ea
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for spi/slink, depending on transfer size,
burst size can be set to 1, 4, or 8.
bug 747979
Original-Change-Id: Ieae0285d374e7d0eb6c2c2e633f8cafbb2b51b3a
Reviewed-on: http://git-master/r/12076
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rf90c38d753a6408ade4312adcd02c574eb3b1a57
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for spi/slink, set dma burst size based on
transfer size.
bug 747979
Original-Change-Id: I8c3c0a0410648a25190847590b9ac0304fb1105f
Reviewed-on: http://git-master/r/11752
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R2549b6684bdb45c0c277f64f0a60de937f406b4e
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This reverts commit 5dba29d1f761502e75320770fc4c6cf9c8e00998.
Rebase-Id: Rb6889e4755716f5baa5c7f272ae7d8c8b6d97ba5
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Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Modified to use syscore_ops
Change-Id: Ic8a3a9559634eb3f1f0e4b40a2d8502d20d606d6
Signed-off-by: Benoit Goby <benoit@android.com>
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Calling the complete callback when a request is cancelled leads to
locking problems in the callback, which could be called from an IRQ
with no locks held, or from whatever context called
tegra_dma_dequeue_req. Instead, expect the caller to handle the
now-cancelled request as needed.
Also removes tegra_dma_dequeue, since all users can be trivially
converted to tegra_dma_dequeue_req.
Change-Id: If699239c09c78d1cd3afa0eaad46535b1d401a24
Signed-off-by: Colin Cross <ccross@android.com>
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"Interrupt during enqueue" happens periodically when the
DMA is almost starving. This happens under certain not-
uncommon scenarios.
Signed-off-by: Iliyan Malchev <malchev@google.com>
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- Added "single buffer continuous DMA" mode in addition to the
"double buffer continuous DMA" mode that is already implemented
- Changed the queuing of next buffer to be more flexible for
continuous DMA. It can now get in-flight right after a transfer
starts, or whenever the client enqueues a buffer.
Signed-off-by: Iliyan Malchev <malchev@google.com>
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Signed-off-by: Iliyan Malchev <malchev@google.com>
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NV_DMA_MAX_TRASFER_SIZE --> TEGRA_DMA_MAX_TRANSFER_SIZE
Signed-off-by: Iliyan Malchev <malchev@google.com>
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Stopping Dma after last req transfer.
add an API to return the completed transfer count of a pending, active
or finished DMA request
originally fixed by Gary King <gking@nvidia.com>
It is observed that the dma interrupt has the lower priority then
its client interupt priority. When client's isr calls dma get transfer,
the dma status has not been upated as dma isr have not been served yet.
So before reading the status, explicitly checking the interrupt status and
handling accordingly.
The another issue which is observed is that if dma has transferred the data
of amount = requested -4 and if it moves to invalid requestor before stopping
then status got reset and tarnsfered bytes becomes 0. This seems the apb dma
hw behavior. Following is the suggestion to overcome this issue:
- Disable global enable bit.
- Read status.
- Stop dma.
- Enable global status bit.
Added this workaround and it worked fine.
originally fixed by Laxman Dewangan <ldewangan@nvidia.com>
In continous mode, dma should stop after last transfer completed and
if there is no more req pending.
If there is pending req then it should check whether it has updated
in hw for next transfer or not and if it has not started then stop dma
and start new req immediatley.
originally fixed by Laxman Dewangan <ldewangan@nvidia.com>
Change-Id: I49c97c96eacdf4060de6b21cec0e71d940d33f00
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Signed-off-by: Iliyan Malchev <malchev@google.com>
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Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: Ibc0b36149bb10baa357a8bb3f24925ce3d6f3d9d
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mach/suspend.h is not used yet, and its functions will be replaced
with syscore ops. Delete it.
Change-Id: I7b32d3514e7f4427c7d5faa97c1954a7a2cc286c
Signed-off-by: Colin Cross <ccross@android.com>
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Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
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tegra_dma_init currently simply bails out early if any initialization fails.
This skips various data-structure initialization. In turn, this means that
tegra_dma_allocate_channel can still hand out channels. In this case, when
tegra_dma_free_channel is called, which calls tegra_dma_cancel, the walking
on ch->list will OOPS since the list's next/prev pointers may still be
NULL.
To solve this, add an explicit "initialized" flag, only set this once _init
has fully completed successfully, and have _allocate_channel refuse to hand
out channels if this is not set.
While at it, simplify _init:
* Remove redundant memsets
* Use bitmap_fill to mark all channels as in-use up-front, and remove
some now-redundant bitmap initialization loops.
* Only mark a channel as free once all channel-related initialization has
completed.
Finally, the successful exit path from _init always has ret==0, so just
hard-code that return. The error path still returns ret.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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The following commit makes the Tegra APB DMA engine fail to initialize
correctly: 0cf6230af909a86f81907455eca2a5c9b8f68fe6
ARM: tegra: Move tegra_common_init to tegra_init_early
The reason is that tegra_init_early_ calls tegra_dma_init which calls
request_threaded_irq, which fails since the IRQ hasn't yet been marked
valid; that only happens in tegra_init_irq, which gets called after
tegra_init_early.
This used to work OK, since tegra_init_early was tegra_common_init, which
got called after tegra_init_irq, basically from the beginning of
tegra_harmony_init.
Solve this by converting tegra_dma_init to a postcore_initcall. This makes
it execute late enough that IRQs are marked valid, and avoids having to
add it back to every machine's init function.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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