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path: root/arch/arm/mach-tegra/dvfs.c
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2012-07-30ARM: tegra: dvfs: enable regulator before using itLaxman Dewangan
The dvfs system require the regulator for regulating the voltage. The regulator should be enable before using it to make sure the reference count enabling rail of that rail should be properly counted. Change-Id: Ib8b673ecb7939ac80f46bdf90ffec27b8f62df6b Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/118598 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-30ARM: tegra: dvfs: Adjust VDD_CPU to offset agingAnshul Jain
Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-06-07ARM: tegra: dvfs: Re-factor CPU alternative dvfsAlex Frid
Removed alternative frequencies table from dvfs structure, and replaced it with table pointer to facilitate future support for multiple alternative tables. Actually supported alternative dvfs table (Tegra3 CPU cold zone table) is not changed. Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/104882 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-19ARM: tegra: dvfs: Add alternative dvfs frequency limitsAlex Frid
Added an option to specify alternative dvfs frequency limits for each tegra clock domain. These alternative limits can be applied in some particularly extreme (e.g., slow) corner of process-temperature space with no effect on regular limits for the rest of the space. Bug 913884 Change-Id: I05e319b60f6dc6f4e7f15c7e677e5a3bce77f201 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/70188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/75614 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-15ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted. Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: dvfs: Fix dvfs over-voltage error handlingAlex Frid
Record dvfs client voltage rate request only after over-voltage error is checked (otherwise, after over-voltage error rail goes above the limit when another client requests voltage change). (cherry picked from commit 9151f77b545dc5b898ad16ceb695cc57764f94e0) Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 40243988e73a13a5c94db410cb0335fa8a9b1e42) Change-Id: I70769b2ffd7303db6e54bfc3e07b47ea3e67b7b8 Reviewed-on: http://git-master/r/64767 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Re82214f06084d58eed67edb35443f7a72ac4d112
2011-11-30ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP modeAlex Frid
Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero, which could happen only while CPU is in LP mode (and CPU regulator output is turned off by side-band signal, anyway): - Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero - Allow VDD_CPU one step change to zero (i.e., to minimum voltage set by constraints) after entry to LP mode - Allow VDD_CPU one step change to the predicted G mode target before exit from LP mode (cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872) (cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827) Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1 Reviewed-on: http://git-master/r/63357 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94
2011-11-30ARM: tegra: dvfs: Enable EMC bridge if rail is disabledAlex Frid
When core rail is disabled it is set to nominal voltage underneath clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe at high voltage that exceeds EMC bridge minimum level. Enable EMC bridge explicitly in this case to set safe floor for EMC. Similarly need to enable EMC bridge when CPU rail is disabled and pushing core voltage (cpu-to-core voltage dependency) over bridge minimum level. (cherry picked from commit bff814b2e46e67defde178b72bd379003b5429c2) (cherry picked from commit e5567cb8dafcbd30797237e7bb91d77ce57de66a) Change-Id: Ibb8dad5132f69e3325d793658b3dcc8b887974bf Reviewed-on: http://git-master/r/62031 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R56f360c3b1ee25bf2dae4b886399b83e357f0225
2011-11-30ARM: tegra: dvfs: Disable all rails if one failed to connectAlex Frid
Change-Id: I0aa4debdb0bed160c6ff9d6e5863bfa06a693017 Reviewed-on: http://git-master/r/55370 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rfb9dea2f471f257a15d9da163226573f5330ce32
2011-11-30ARM: tegra: dvfs: Retry rail updateAlex Frid
Since rail voltage change may be limited by from-relationship with another rail, retry rail update to account for circular dependencies. Bug 864112 Original-Change-Id: Ie45f656a74eac925ab2383fbe620fad47742d02f Reviewed-on: http://git-master/r/47233 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R8f9435fb610c27605cdc043ebf2ef13a29377c3d
2011-11-30ARM: tegra: clock: Add Tegra3 emc high voltage bridgeAlex Frid
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz can not work at high core voltage; the intermediate step (bridge) is mandatory when core voltage is crossing the 1.2V threshold (fixed for Tegra3 arch). In addition emc must run above bridge rate if any other than emc clock requires high voltage. EMC bridge is implemented as a special emc shared user: its rate is set once during emc dvfs table initialization; then, the bridge is enabled or disabled when sbus and/or cbus voltage requirement is crossing the threshold (sbus and cbus together include all clocks that may require voltage above threshold - other peripherals can reach their maximum rates below threshold). Bug 846693 Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf Reviewed-on: http://git-master/r/39919 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
2011-11-30ARM: tegra: dvfs: Fix uninitialized variable useAlex Frid
Completing fix started by 68e857d94f35286b9b359feef1e1dddc7e2aea8b. Original-Change-Id: I61e9051da3d7aacd460d15ef8ff161b678c8fec1 Reviewed-on: http://git-master/r/32829 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Tested-by: David Schalig <dschalig@nvidia.com> Rebase-Id: R352e5430825dd246eb7c8242b78f04699273f8e6
2011-11-30tegra: dvfs: fix unintialized variable useDavid Schalig
Assignment moved inside if statement, where it belongs. bug 828756 Original-Change-Id: I6e1c621a8c4d64b9b5a43df1e79992863fe3d514 Reviewed-on: http://git-master/r/31984 Reviewed-by: David Schalig <dschalig@nvidia.com> Tested-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R6c935302ff60ed4029d4cb775cf2b851418577ca
2011-11-30ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R30393515042d199154ba708afaefb134402f551a
2011-11-30ARM: tegra: restore voltage to nominal when rebootBo Yan
At the time of reboot, all rails need to be set to nominal to ensure the success of subsequent boot. bug 821969 bug 797082 Original-Change-Id: Iee635c222619dfcb3e98f13e665ea2bd04e94245 Reviewed-on: http://git-master/r/30086 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Racbc707a55e92261310e956707a850df1db00f72
2011-11-30ARM: tegra: power: Add Tegra3 CPU/CORE rails dependenciesAlex Frid
On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range. Updated tegra dvfs accordingly, and resolved circular dependencies between CPU and CORE rails created by this requirement. Original-Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539 Reviewed-on: http://git-master/r/29935 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R6aa2bc61513ab16c4551ebeb193e01803501f596
2011-11-30(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updatingDiwakar Tundlam
Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f Reviewed-on: http://git-master/r/26630 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d
2011-11-30ARM: tegra: Add dvfsColin Cross
Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 20:06:07 +0000