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On Tegra3 platforms emc configurations for DDR3 rates below 300MHz
can not work at high core voltage; the intermediate step (bridge) is
mandatory when core voltage is crossing the 1.2V threshold (fixed for
Tegra3 arch). In addition emc must run above bridge rate if any other
than emc clock requires high voltage.
EMC bridge is implemented as a special emc shared user: its rate is set
once during emc dvfs table initialization; then, the bridge is enabled
or disabled when sbus and/or cbus voltage requirement is crossing the
threshold (sbus and cbus together include all clocks that may require
voltage above threshold - other peripherals can reach their maximum
rates below threshold).
Bug 846693
Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf
Reviewed-on: http://git-master/r/39919
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
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Completing fix started by 68e857d94f35286b9b359feef1e1dddc7e2aea8b.
Original-Change-Id: I61e9051da3d7aacd460d15ef8ff161b678c8fec1
Reviewed-on: http://git-master/r/32829
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Rebase-Id: R352e5430825dd246eb7c8242b78f04699273f8e6
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Assignment moved inside if statement, where it belongs.
bug 828756
Original-Change-Id: I6e1c621a8c4d64b9b5a43df1e79992863fe3d514
Reviewed-on: http://git-master/r/31984
Reviewed-by: David Schalig <dschalig@nvidia.com>
Tested-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R6c935302ff60ed4029d4cb775cf2b851418577ca
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For different Tegra3 process corners/skus/revisions/boards set nominal
voltages for CPU and core rails as well as adjust maximum clock rates
as follows.
- VDD_CORE rail nominal voltage: default value is indexed by speedo_id
of the chip (speedo_id is determined by chip sku and revision). Minimum
of the default and board specific electrical design voltage is rounded
down against core dvfs voltage ladder. The result is set as nominal
core voltage (edp voltage API is not implemented, yet).
- VDD_CPU rail nominal voltage: default value is indexed by speedo_id
of the chip. If too high, it is lowered to core nominal voltage so that
core_on_cpu dependency is resolved at nominal core level. The result is
compared with voltage required to reach CPU maximum rate as specified
in the dvfs table for the particular process corner. Again, the minimal
level is selected, and finally set as CPU nominal voltage.
After nominal voltages are determined, maximum rate for each dvfs clock
is adjusted accordingly, so that it does not exceed the rate specified
in the respective DVFS table at nominal level.
Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3
Reviewed-on: http://git-master/r/30928
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Rebase-Id: R30393515042d199154ba708afaefb134402f551a
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At the time of reboot, all rails need to be set to nominal to ensure
the success of subsequent boot.
bug 821969 bug 797082
Original-Change-Id: Iee635c222619dfcb3e98f13e665ea2bd04e94245
Reviewed-on: http://git-master/r/30086
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Racbc707a55e92261310e956707a850df1db00f72
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On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range.
Updated tegra dvfs accordingly, and resolved circular dependencies
between CPU and CORE rails created by this requirement.
Original-Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539
Reviewed-on: http://git-master/r/29935
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: R6aa2bc61513ab16c4551ebeb193e01803501f596
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Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f
Reviewed-on: http://git-master/r/26630
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb
Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d
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Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f
Signed-off-by: Colin Cross <ccross@android.com>
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