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path: root/arch/arm/mach-tegra/dvfs.h
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2012-07-30ARM: tegra: dvfs: Adjust VDD_CPU to offset agingAnshul Jain
Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-20ARM: tegra: dvfs: add back 916mV & 1007mV entriesPeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/113751 (cherry picked from commit 833f9d47a350358000e9201f77a3c9fd655d2900) Change-Id: I679093d9d2577625bff3e02e25ffe90d396ea5a6 Reviewed-on: http://git-master/r/116134 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-20ARM: tegra: dvfs: update Tegra3 single-core dvfs tablePeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/110587 (cherry picked from commit c0e7904245168cafc426219948ab132a4d832376) Change-Id: I370f4af1d4ce888ebc71351519c1018b82d91913 Reviewed-on: http://git-master/r/116132 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-19ARM: tegra: dvfs: Handle Tegra3 alternative dvfs errorsRohan Somvanshi
Propagate error to the caller when switching between alternative cpu dvfs tables. Change dvfs table during cpu hotplug operation only after the new edp limit is set, and abort bringing cpu core on-line in case of failure in applying new (less conservative) table. When cpu core is removed change dvfs table before setting new edp limit, and ignore error (it is safe to continue with more conservative table). Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b) Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271 Reviewed-on: http://git-master/r/114779 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-07ARM: tegra: dvfs: Alter CPU dvfs on EDP eventsAlex Frid
Extended EDP processing of cpu up/down events with calls to alter CPU dvfs table. This is in addition to already supported changing of CPU dvfs on EDP thermal event. For now, added calls do not actually alter the table. Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/104883 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-07ARM: tegra: dvfs: Re-factor CPU alternative dvfsAlex Frid
Removed alternative frequencies table from dvfs structure, and replaced it with table pointer to facilitate future support for multiple alternative tables. Actually supported alternative dvfs table (Tegra3 CPU cold zone table) is not changed. Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/104882 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-16Arm: p1852: dvfs: Added ASIC SKUs as per updated PORMohit Kataria
Automotive platforms are broken down further into 5 Asic skus from 3 ASIC SKUs, updated kernel to reflect these changes. Bug 983555 Change-Id: I75925c5853d4ec2a5c72e430f4c2380e58aae774 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/101903 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-01-19ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limitsAlex Frid
Added alternative frequency limits for Tegra3 CPU. These limits are applied only in the lowest CPU EDP temperature zone, and the offset from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling voltage steps. Offset values as well as temperature threshold are to be updated per characterization. Bug 913884 Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/70189 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/75615 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-19ARM: tegra: dvfs: Add alternative dvfs frequency limitsAlex Frid
Added an option to specify alternative dvfs frequency limits for each tegra clock domain. These alternative limits can be applied in some particularly extreme (e.g., slow) corner of process-temperature space with no effect on regular limits for the rest of the space. Bug 913884 Change-Id: I05e319b60f6dc6f4e7f15c7e677e5a3bce77f201 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/70188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/75614 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-12-15ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted. Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP modeAlex Frid
Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero, which could happen only while CPU is in LP mode (and CPU regulator output is turned off by side-band signal, anyway): - Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero - Allow VDD_CPU one step change to zero (i.e., to minimum voltage set by constraints) after entry to LP mode - Allow VDD_CPU one step change to the predicted G mode target before exit from LP mode (cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872) (cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827) Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1 Reviewed-on: http://git-master/r/63357 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94
2011-11-30ARM: tegra: dvfs: Enable EMC bridge if rail is disabledAlex Frid
When core rail is disabled it is set to nominal voltage underneath clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe at high voltage that exceeds EMC bridge minimum level. Enable EMC bridge explicitly in this case to set safe floor for EMC. Similarly need to enable EMC bridge when CPU rail is disabled and pushing core voltage (cpu-to-core voltage dependency) over bridge minimum level. (cherry picked from commit bff814b2e46e67defde178b72bd379003b5429c2) (cherry picked from commit e5567cb8dafcbd30797237e7bb91d77ce57de66a) Change-Id: Ibb8dad5132f69e3325d793658b3dcc8b887974bf Reviewed-on: http://git-master/r/62031 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R56f360c3b1ee25bf2dae4b886399b83e357f0225
2011-11-30ARM: tegra: power: Add Tegra3 balanced throttlingAlex Frid
Balanced CPU and core domains thermal throttling on Tegra3. When throttling is enabled the new algorithm caps core bus frequencies (EMC, cbus and sbus) along with CPU rate. The throttling steps, and time spent on each step are pre-defined based on characterization results. (cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e) (cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f) Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f Reviewed-on: http://git-master/r/61024 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190
2011-11-30ARM: tegra: clock: Add Tegra3 emc high voltage bridgeAlex Frid
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz can not work at high core voltage; the intermediate step (bridge) is mandatory when core voltage is crossing the 1.2V threshold (fixed for Tegra3 arch). In addition emc must run above bridge rate if any other than emc clock requires high voltage. EMC bridge is implemented as a special emc shared user: its rate is set once during emc dvfs table initialization; then, the bridge is enabled or disabled when sbus and/or cbus voltage requirement is crossing the threshold (sbus and cbus together include all clocks that may require voltage above threshold - other peripherals can reach their maximum rates below threshold). Bug 846693 Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf Reviewed-on: http://git-master/r/39919 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
2011-11-30arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2011-11-30ARM: tegra: dvfs: Update DVFS tables with data for T30SDiwakar Tundlam
Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809 Reviewed-on: http://git-master/r/34381 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R318f6916f8213c25092110a8800eb506d1718b38
2011-11-30ARM: tegra: clocks: Completely remove DVFS for FPGA platformsScott Williams
Dynamic Voltage & Frequency Scaling (DVFS) is not possible on FPGA platforms. Completely remove the DVFS code from the image on FPGA platforms to reduce the image size. Original-Change-Id: I4f1a8587f01e775000f48fbca7c85d75acee9c74 Reviewed-on: http://git-master/r/32466 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R08c78dd7e7bfe891a3d48de16f5a863ad5d07999
2011-11-30ARM: tegra: power: Add Tegra3 CPU/CORE rails dependenciesAlex Frid
On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range. Updated tegra dvfs accordingly, and resolved circular dependencies between CPU and CORE rails created by this requirement. Original-Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539 Reviewed-on: http://git-master/r/29935 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R6aa2bc61513ab16c4551ebeb193e01803501f596
2011-11-30(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updatingDiwakar Tundlam
Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f Reviewed-on: http://git-master/r/26630 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: dvfs: Expand CPU voltage scaling tablesAlex Frid
Added CPU DVFS tables for new tegra2 revisions/skus. Implemented table selection based on chip speedo and process corner. Original-Change-Id: Ic2aa7ff2b487a37a0a97d4f40453ff033a562207 Reviewed-on: http://git-master/r/13397 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd090645567dbff203637e72fef3ead73019b4dcf
2011-11-30ARM: tegra: Add dvfsColin Cross
Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-27 20:31:38 +0000