summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/include/mach/clk.h
AgeCommit message (Collapse)Author
2012-07-01ARM: tegra: emc: add reference counting to early ack disablementSang-Hun Lee
Bug 995950 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/110190 (cherry picked from commit cbfc31fb126cd651157125d1785135eced6587dd) Change-Id: I44eb889235db82b0efda238b87be5612425afb9d Reviewed-on: http://git-master/r/110978 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-15ARM: tegra: clock: Add tegra_cpu_user_cap_set functionJinyoung Park
To set cpu_user_cap in tegra drivers, added tegra_cpu_user_cap_set function. Bug 945552 Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com> Reviewed-on: http://git-master/r/87109 (cherry picked from commit db954aafdfdbe1fa122466b8e8ec4ea4273efb90) Change-Id: I765c44de4ed4ae908ef56914db53533605bd6d88 Reviewed-on: http://git-master/r/89740 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-11-30ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
2011-11-30arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2011-11-30ARM: tegra: clock: Add clock rate change notificationAlex Frid
Original-Change-Id: I97434334a4214180a365d9709a331405da135669 Reviewed-on: http://git-master/r/36202 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a
2011-11-30ARM: tegra: clocks: Completely remove DVFS for FPGA platformsScott Williams
Dynamic Voltage & Frequency Scaling (DVFS) is not possible on FPGA platforms. Completely remove the DVFS code from the image on FPGA platforms to reduce the image size. Original-Change-Id: I4f1a8587f01e775000f48fbca7c85d75acee9c74 Reviewed-on: http://git-master/r/32466 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R08c78dd7e7bfe891a3d48de16f5a863ad5d07999
2011-11-30Update copyrightsScott Williams
Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
2011-11-30ARM: tegra: clock: Re-factor extended clock operationsAlex Frid
Re-factored extended clock operations to enumerate configuration parameters. Original-Change-Id: I6c1e5f07803a8e6da0ebd6690892f50bb59efcd5 Reviewed-on: http://git-master/r/15144 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I25147998969b385905bad5eb3ceb2dbb89c0d93a Rebase-Id: R815ccca27fac9a0af334c188ce77e0ec4fdad9b2
2011-11-30ARM: tegra: clock: Add extended clock configurationAlex Frid
Some peripheral clock source registers have extra bits with setting specific for the respective controller. Added mechanism to manipulate these bits from the clock code with proper locking. Implemented NAND, VI and DTV extended configurations. Original-Change-Id: Ic8a1887923f0b98f9b1fac06dcf4f90084b017c0 Reviewed-on: http://git-master/r/15059 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Original-Change-Id: Ic3416be8683c90043376d6675269fc23e440f61d Rebase-Id: Rd3e7af5a00bf9580816853456ddb6f19b9bc5b2b
2011-11-30ARM: tegra: Add dvfsColin Cross
Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f Signed-off-by: Colin Cross <ccross@android.com>
2011-02-21ARM: tegra: clock: Add function to set SDMMC tap delayColin Cross
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
2011-02-21ARM: tegra: clock: Convert global lock to a lock per clockColin Cross
Give each clock its own lock, and remove all lock traversals from parent to child clocks to prevent AB-BA deadlocks. This brings the locking in line with the common struct clk patches and should make conversion simple. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
2011-02-21ARM: tegra: clock: Drop CPU dvfsColin Cross
The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
2011-01-26ARM: tegra: clock: Add forward reference to struct clkColin Cross
Signed-off-by: Colin Cross <ccross@android.com>
2010-10-21[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
2010-08-05[ARM] tegra: Add clock supportColin Cross
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 05:54:24 +0000