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path: root/arch/arm/mach-tegra/include/mach/pinmux.h
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2012-01-04ARM: tegra: pinmux: Support for setting pin ioPradeep Goudagunta
-Added support for setting a pin io state to INPUT/OUTPUT. -Exported tegra_pinmux _get_pingroup/_set_io to make them available to loadable kernel modules. Bug 845065 Change-Id: I7d9500f590b804d1d222dfd7e42d1dbfc6686611 Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-on: http://git-master/r/71975 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-21arm: tegra: Use generator macros for pinmux selectorsScott Williams
Replace the hand-crafted pinmux mux selector enumerators and name table with generator macros to avoid mismatches between them. Change-Id: I2e56bf89a4b29f33af00d0e4d2617ee13c554997 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/70088 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2011-11-30Arm: Tegra: Cardhu: Set slew rise/fall rates properlyPavan Kunapuli
Setting the slewrise and slewfall rates properly. Bug 811303 Reviewed-on: http://git-master/r/52367 (cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031) Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836 Reviewed-on: http://git-master/r/62326 (cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9) Reviewed-on: http://git-master/r/63813 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
2011-11-30ARM: tegra: gpio: Set a gpio to tristate or normalChaitanya Bandi
Create mapping from gpio to pingroup and set gpio to normal or tristate Bug 866633 Reviewed-on: http://git-master/r/56557 (cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115) Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21 Reviewed-on: http://git-master/r/61120 Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e
2011-11-30ARM: tegra: Update copyrightsScott Williams
Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/51157 Rebase-Id: R795bf03590a76b6c494afd37603ed951dc2cd082
2011-11-30ARM: Tegra: Pinmux: Fix drive strength configurationPavan Kunapuli
In T30, different pad ctrl group registers have different pull up and pull down drive strength field offsets and maximum values. Modified drive_strength structure to be able to pass the offsets and masks of each group to ensure that drive strengths are properly configured. Bug 870369 Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704 Reviewed-on: http://git-master/r/49872 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd
2011-11-30ARM: tegra: Fix modpost warningScott Williams
Change-Id: I69f9b9f74a98ef31f496478e48896dc51044a72e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49273 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf384c1b08e441df3a7aeb4bba86a78da1663a7d2
2011-11-30ARM: Tegra: Cardhu: Setting sdmmc drive strengthsnaveenk
configuring sdmmc drive strengths as suggested by HW team based on Characterization results Bug 799568 Original-Change-Id: Id30505659aefb9c63a24f8baa8296a62723710b4 Reviewed-on: http://git-master/r/46949 Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R4d0b228317fd12c185b735ed248818f5217d9ed4
2011-11-30arm: tegra3: Keep DAP2 in maximum driver strengthLaxman Dewangan
Setting maximum driver strength of DAP2 in all tegra3 based system by default. bug 820361 Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a Reviewed-on: http://git-master/r/44497 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321
2011-11-30ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PMScott Williams
For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration parameter to use on Tegra for power management, and not CONFIG_PM. CONFIG_PM does not have the required dependency on CONFIG_SUSPEND necessary to pull in the CPU suspend/resume functionality used by Tegra. Also fixes compilation errors when CONFIG_PM and by implication CONFIG_PM_SLEEP are not configured. Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad Reviewed-on: http://git-master/r/40458 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
2011-11-30arm: tegra: Clean up SOC conditionalsScott Williams
Change SOC conditionals to make them more forward-looking. Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9 Reviewed-on: http://git-master/r/32706 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998
2011-11-30arm: tegra3: Updating pinmux table based on TRMLaxman Dewangan
On tegra3 TRM, some of the pin mux option for a given pin group is not recommended and so not exposed in the TRM reference table. Updating the pinmux table accordingly. The non-recommended pin option is set as TEGRA_MUX_INVALID. bug 817099 Original-Change-Id: I572ee84912fe065a73e59d4f9ba0ce01223ead85 Reviewed-on: http://git-master/r/29626 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R88ad8a84c4516c8692b9266d6c073f20e35b420e
2011-11-30arm: tegra: pinmux: Supporting LOCK/OD/IORESET pin configuration.Laxman Dewangan
Supporting the LOCK, OpenDrain (OD), IO_RESET configuration on pinmux register through pinmux apis. Original-Change-Id: I2459723c5fbcadd925331696c9469f64d2ba3b20 Reviewed-on: http://git-master/r/17532 Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Original-Change-Id: Ibd06c9a650ffbacf51530514e58bd52d1f60b4f2 Rebase-Id: R8e593a0b1e27db641d2e0c7b57a2946d97819f25
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: clocks: Add mux clock inputs to cdev1 and cdev2Jin Park
For getting actual rate, add mux clock inputs to cdev1 and cdev2. Change-Id: Ic42eb97a51bceb5249ca29938ac00f8add9ef032 Signed-off-by: Jin Park <jinyoungp@nvidia.com> Reviewed-on: http://git-master/r/23187 Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rae9706a85a80f4cd8cf724c6d0adf97694138f70
2011-11-30ARM: tegra: pinmux: Convert suspend/resume to syscoreColin Cross
Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I3228600e93f819821b13b0955961fc1cbfb826a8
2010-10-21[ARM] tegra: pinmux: add safe values, move tegra2, add suspendColin Cross
- the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral - also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control - add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups) - move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code - fix debug output for group with no pullups - add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks. Signed-off-by: Gary King <gking@nvidia.com>
2010-08-05[ARM] tegra: add pinmux supportErik Gilling
v2: fixes from Russell King - include linux/io.h instead of asm/io.h v3: - Add drive strength controls - Replace typedef enums with plain enums Signed-off-by: Erik Gilling <konkers@android.com> Signed-off-by: Colin Cross <ccross@android.com>
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