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Add functionality to enable changing of latency
allowance settings. This is used for memory
tables that may have different tick lengths.
Bug 955082
Change-Id: I3055a062846cfdeb992931e691cf687ffb05725c
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/124979
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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This is necessary to support future tegra SOC's.
Change-Id: I2f6ce328e30a6895dce16d82c4097291339155cd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/123146
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Remove the ad-hoc scale factor of final latency allowance.
Scale the fifo size to pretend that our FIFO is only as deep
as the lowest fullness we expect to see.
Bug 995270
Change-Id: I78ed2246d2031a2303f81a19fe05c95572a692b0
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-on: http://git-master/r/118816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Tested-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Decrease the priority for 2D operations so they do not compete with display.
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/76683
(cherry picked from commit 2094d7c0b435b8a22c81a4bc5d54d4a697518f3a)
Change-Id: Id559a585a4826a370850c893fda21f47ab339019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/79994
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Reviewed-on: http://git-master/r/76065
Change-Id: I8eb5148399cc8a08c2f37f20927b655f3e909241
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76817
Reviewed-by: Automatic_Commit_Validation_User
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Requesting to set LA for zero bandwidth would otherwise
cause division by zero exception in LA computation. LA can
safely be set to max in this case.
Original-Change-Id: Id234e2432c7c21b7ab3d13614d0f9fbd82199cde
Reviewed-on: http://git-master/r/47132
Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com>
Tested-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R58676140d46d2b7b2b2c117a03f088944a8f4382
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arch/arm/mach-tegra/latency_allowance.c:499: warning: format '%4u'
expects type 'unsigned int', but argument 4 has type 'long unsigned int'
Original-Change-Id: Idfea3e60da375bfe903e1a517505c727ecc83d72
Reviewed-on: http://git-master/r/46495
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R8eeb5ccc518d9591fa1a9a521913b17ec28c6b52
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In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.
Bug 840688
Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1
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add /sys/kernel/debug/tegra_latency/la_info to print programmed latency
allowance settings.
Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77
Reviewed-on: http://git-master/r/42285
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09
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Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91
Reviewed-on: http://git-master/r/36570
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9
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