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path: root/arch/arm/mach-tegra/latency_allowance.c
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2014-05-13arm: tegra12: la: detect when disp la < min laAdeel Raza
Detect when a display client's new LA value is less than the minimum LA for the current EMC frequency. Return an error in such a case and let the display driver take corrective action. Bug 1495454 Bug 1486711 Change-Id: I8bda8a01cc657e3774213a5e2e6dd38f21220010 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/401696 (cherry picked from commit d161832ca7a48fe958677e5520a6aab49c50f004) Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-on: http://git-master/r/404641 GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2014-05-06tegra: Remove old SOC/Board supportDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I06582980f2e9e88ab0e34bc5febc5d939fb77cc4 Reviewed-on: http://git-master/r/404934 (cherry picked from commit d1095251dadc17cb2c4f885f0d5d23359536f02b) Reviewed-on: http://git-master/r/405472 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-03-24arm: tegra12: la: use correct DVFS time functionAdeel Raza
Use the correct function to query the DVFS clock change latency value. Bug 1327082 Change-Id: Iea3be2907e2edbc59cdfcc28f7567568b163273f Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/384486 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2014-01-22arm: tegra: la: use tegra12x code for tegra13xAdeel Raza
Bug 1432587 Change-Id: If406f6d108eef80c094b40bd5878001f4f6be20c Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/350790 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chao Xu <cxu@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2013-10-23arm: tegra: la: add t12x camera la supportAdeel Raza
Bug 1381431 Change-Id: I12129c6d8b3e786c637351e4890af659e2654297 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/289995 Reviewed-by: Bruce Holmer <bholmer@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-10-17arm: tegra: build only one tegra*_la.c fileMatt Craighead
This slightly reduces the kernel's size and build time and is more consistent with how other files are handled in the makefile. Bug 1351594 Change-Id: I087263f0e1d9afa1fa844a337b1823ddc8cbfa80 Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/299058 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
2013-10-15arm: tegra: la: program bbc ptsa dynamicallyKrishna Reddy
program bbc ptsa dynamically based on bw requested for BBCR and BBCW add sysfs nodes to disable display, bbc ptsa's. Bug 1322650 Change-Id: I8dbb9445c1fa9ca32072c77a9193164925aaa8da Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/272179 (cherry picked from commit 0ec1afbc0d38fbbe3a86542169f137d6c4241ae3) Reviewed-on: http://git-master/r/294241 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
2013-10-03arm: tegra: fix compile warning latency_allowance.cPhilip Rakity
min requries that types match Change-Id: Iee9203f1d2bc6694194e3cbc2221052bb463fd35 Signed-off-by: Philip Rakity <prakity@nvidia.com> Reviewed-on: http://git-master/r/269685 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> (cherry picked from commit d8d29f9e86ced222f2dd55f74e38158f09daf837) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-09-14ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>Dan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
2013-09-14ARM: tegra: Use <linux/clk/tegra.h> instead of <mach/clk.h>Dan Willemsen
So that the upstream common clk infrastructure can live side by side. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I0fe0ef8cd207d27b707821eed838c75b8ec04025
2013-09-14arm: tegra: la: add t12x la driverAdeel Raza
Bug 1224933 Change-Id: I2dd8beab87d91c9558a360a73e51be0dc7b016c1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/257190 Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-09-14arm: tegra: la: restore ptsa and la to values to same as before suspendKrishna Reddy
add support to disable display la and ptsa updates. add chip specific la and ptsa resume support. Change-Id: Ib1fed1829187a3a23426c3f7dfaf838fbd780de0 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/202087 (cherry picked from commit eef6b14b98044c56b444bd824a0eb63f5393ba48) Reviewed-on: http://git-master/r/204317 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
2013-09-14arm: tegra: la: restore la and ptsa during resumeKrishna Reddy
resore la and ptsa to boot values during resume. remove unnecessary code. Change-Id: Ib7c3e9b0627572620fa4df08967da18d7473baa8 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/201250 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14arm: tegra: la: la and ptsa updates for t14x.Krishna Reddy
Change-Id: I31ede6f4f3e98b26f1ac1d96068cb6c0c6d0ad15 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/197530 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2013-09-14ARM: tegra: Build latency allowance in pre-si buildJeff Smith
Disable at run time on unsupported platforms. Change-Id: I84a6eb7540f85a40b4b86ac224232fa07dcdb273 Signed-off-by: Jeff Smith <jsmith@nvidia.com> Reviewed-on: http://git-master/r/161706 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14fixup latency_allowance mach/io[map].h not neededDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14arm: tegra: la: refactor la code.Krishna Reddy
refactor it to detect soc at run and work. Change-Id: I0677367384df8bf3378b3e09c26aaa9b70f2cb2f Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/190449 Reviewed-by: Harshada Kale <hkale@nvidia.com> Tested-by: Harshada Kale <hkale@nvidia.com>
2013-09-14arm: tegra: add config option for tegra errata 977223.Krishna Reddy
Enable the errata for t11x and update latency allowance code with WAR for errata. Bug 977223 Change-Id: I1a825f0fe3252a2c9f4e69a591970c4373f72fa6 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/169773 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14arm: tegra: la: add latency allownace support for t14x.Krishna Reddy
Change-Id: I8bf612496e2a5c5e12db80d70d51f3341fd31b02 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/162102 Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14arm: tegra: mc: add config option for PTSA.Krishna Reddy
Add config option for MC PTSA enable/disable. Move T11x specific registers to t11x file. Change-Id: I48a7013937faffdf99b1f54135b0b06da961b156 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/143901 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: Ra60e4393cc04d0d4d7c6eee91dea12c7736fc103
2013-09-14arm: tegra: la: Program PTSA registers in LA moduleKrishna Reddy
Change-Id: Iaeac46499af6df3550bf000056b93cc474a9b483 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/139556 (cherry picked from commit 64900b9a27845b201002b07bf7b8537a682f3d38) Reviewed-on: http://git-master/r/143786 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R9b26f42a60597b117e14c92c03727cc27042ba08
2013-09-14arm: tegra: la:Add support to set initial static LA valuesKrishna Reddy
Change-Id: I6820aeeb4105509f8ede185c4418c384ad0d91b3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/138721 (cherry picked from commit e42ebbd79029066a30c0b94a3ad1c3055dde3e2f) Reviewed-on: http://git-master/r/143785 Reviewed-by: Alex Waterman <alexw@nvidia.com> Rebase-Id: Rfb09e3e7ff2460924e0ebd2dcece4db5319c1f8e
2013-09-14arm: tegra: la: Convert error message to WARN_ONCEKrishna Reddy
Change-Id: Ie11de7963ea9c9538d6c6a2db971c47f66eb0912 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/138720 (cherry picked from commit 8a9ab8c39e09ab7e9bea494b7f585a6cba7258dd) Reviewed-on: http://git-master/r/143783 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R71917ffcdf7db63c2298b1d787e3d72b027d73b6
2013-09-14arm: tegra: la: Add latency allowance support for T11x.Krishna Reddy
Change-Id: If204129a17041601beba04192eb58bb10c11e1c5 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/130571 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Rebase-Id: R6e3607d1e9e0a6a138129463a3659ad3547cee21
2013-09-14arm: tegra: la: Add config option for latency allowance scalingKrishna Reddy
Change-Id: I90d7fd87e774e04f8d671dfcec5f1833871c7ef9 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/130403 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Re780070ae179523c97dd833555dc9f1bceead353
2013-09-14ARM: tegra: fix dalmore-t114 compilation errorsaghuge
Bug 1035282 Change-Id: I6e158ce88a8cce4818fe6ec633b1bb58564d8b18 Signed-off-by: aghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/129834 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R635eff3c24ce6b5ad1e5627e61fb8da4f72cd374
2013-09-14ARM: tegra: la: add function to scale LARay Poudrier
Add functionality to enable changing of latency allowance settings. This is used for memory tables that may have different tick lengths. Bug 955082 Change-Id: I3055a062846cfdeb992931e691cf687ffb05725c Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/124979 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R243cded2f4afaf90b1efa39e1014cad80637fe25
2013-09-14ARM: Tegra: la: do not compile driver for Tegra2Varun Wadekar
Change-Id: I6120ce75b91efff29e24a60546f50f1767271bd8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Re085312717df63bd54fc154589bfb2bc8a19a441
2013-09-14arm: tegra: la: refactor la code.Krishna Reddy
This is necessary to support future tegra SOC's. Change-Id: I2f6ce328e30a6895dce16d82c4097291339155cd Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/123146 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R76c046610a6744d62363529a2162bc8c1e04d56c
2013-09-14arm: tegra: la: hack latency allowance formulaMichael Frydrych
Remove the ad-hoc scale factor of final latency allowance. Scale the fifo size to pretend that our FIFO is only as deep as the lowest fullness we expect to see. Bug 995270 Change-Id: I78ed2246d2031a2303f81a19fe05c95572a692b0 Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com> Reviewed-on: http://git-master/r/118816 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com> Tested-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: R32a6b53f3eed710c019b14d30703c58f8e7c5852
2013-09-14ARM: Tegra: fix compilation warningsVarun Wadekar
Change-Id: I00c67d6ec68c7566c2764aa8d135c101bacc17d7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R09f4e594dc2d50c3bec9c4cb6e2f5982b8861bff
2013-09-14ARM: tegra: la: fix compilations errors for T2Varun Wadekar
Change-Id: Ia61054f13fee9bcefaa290364297bbaeaa725110 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R55e6600e11ac7e10d2717f543497d5fa748774de
2013-09-14arm: tegra: la: change default LA for 2DJon Mayo
Decrease the priority for 2D operations so they do not compete with display. Signed-off-by: Jon Mayo <jmayo@nvidia.com> Reviewed-on: http://git-master/r/76683 (cherry picked from commit 2094d7c0b435b8a22c81a4bc5d54d4a697518f3a) Change-Id: Id559a585a4826a370850c893fda21f47ab339019 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/79994 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Rebase-Id: Rf5b073de01845748b038e55922c7be299c73cc90
2013-09-14arm: tegra: la: Fix the register offset for G2_1Krishna Reddy
Reviewed-on: http://git-master/r/76065 Change-Id: I8eb5148399cc8a08c2f37f20927b655f3e909241 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76817 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: R0bb294468ebbc74fb13036c69134143c5c9d3323
2013-09-14ARM: tegra: la: set LA to max for zero bandwidth requestsMichael Frydrych
Requesting to set LA for zero bandwidth would otherwise cause division by zero exception in LA computation. LA can safely be set to max in this case. Original-Change-Id: Id234e2432c7c21b7ab3d13614d0f9fbd82199cde Reviewed-on: http://git-master/r/47132 Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com> Tested-by: Michael Frydrych <mfrydrych@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R58676140d46d2b7b2b2c117a03f088944a8f4382
2013-09-14ARM: tegra: la: remove printf warningJon Mayo
arch/arm/mach-tegra/latency_allowance.c:499: warning: format '%4u' expects type 'unsigned int', but argument 4 has type 'long unsigned int' Original-Change-Id: Idfea3e60da375bfe903e1a517505c727ecc83d72 Reviewed-on: http://git-master/r/46495 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R8eeb5ccc518d9591fa1a9a521913b17ec28c6b52
2013-09-14ARM: tegra: la: use lower LA for display clientsJon Mayo
In order to prevent display underflow until latency allowance scaling is enabled, use the LA value corresponding to low threshold, instead of max LA for full FIFO. Bug 840688 Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a Reviewed-on: http://git-master/r/46342 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Kevin Huang <kevinh@nvidia.com> Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1
2013-09-14ARM: tegra: la: Add debugfs to latency allowance.Jon Mayo
add /sys/kernel/debug/tegra_latency/la_info to print programmed latency allowance settings. Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77 Reviewed-on: http://git-master/r/42285 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09
2013-09-14ARM: tegra: la: Add support for latency allowance.vdumpa
Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91 Reviewed-on: http://git-master/r/36570 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-18 03:25:58 +0000