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Add config option for MC PTSA enable/disable.
Move T11x specific registers to t11x file.
Change-Id: I48a7013937faffdf99b1f54135b0b06da961b156
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/143901
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Change-Id: Iaeac46499af6df3550bf000056b93cc474a9b483
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/139556
(cherry picked from commit 64900b9a27845b201002b07bf7b8537a682f3d38)
Reviewed-on: http://git-master/r/143786
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Change-Id: I6820aeeb4105509f8ede185c4418c384ad0d91b3
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/138721
(cherry picked from commit e42ebbd79029066a30c0b94a3ad1c3055dde3e2f)
Reviewed-on: http://git-master/r/143785
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Change-Id: Ie11de7963ea9c9538d6c6a2db971c47f66eb0912
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/138720
(cherry picked from commit 8a9ab8c39e09ab7e9bea494b7f585a6cba7258dd)
Reviewed-on: http://git-master/r/143783
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: If204129a17041601beba04192eb58bb10c11e1c5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/130571
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Change-Id: I90d7fd87e774e04f8d671dfcec5f1833871c7ef9
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/130403
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 1035282
Change-Id: I6e158ce88a8cce4818fe6ec633b1bb58564d8b18
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/129834
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Add functionality to enable changing of latency
allowance settings. This is used for memory
tables that may have different tick lengths.
Bug 955082
Change-Id: I3055a062846cfdeb992931e691cf687ffb05725c
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/124979
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Change-Id: I6120ce75b91efff29e24a60546f50f1767271bd8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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This is necessary to support future tegra SOC's.
Change-Id: I2f6ce328e30a6895dce16d82c4097291339155cd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/123146
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Conflicts:
arch/arm/boot/compressed/Makefile
arch/arm/boot/compressed/atags_to_fdt.c
arch/arm/boot/compressed/head.S
arch/arm/boot/dts/tegra30.dtsi
arch/arm/include/asm/bug.h
arch/arm/kernel/traps.c
arch/arm/mach-tegra/Makefile.boot
arch/arm/mach-tegra/board-cardhu-sdhci.c
arch/arm/mach-tegra/board-cardhu.c
arch/arm/mach-tegra/board-enterprise-sdhci.c
arch/arm/mach-tegra/board-enterprise.c
arch/arm/mach-tegra/board-harmony.c
arch/arm/mach-tegra/board-kai-sdhci.c
arch/arm/mach-tegra/board-ventana.c
arch/arm/mach-tegra/board-whistler.c
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/fuse.h
arch/arm/mach-tegra/tegra2_usb_phy.c
arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/tegra3_dvfs.c
arch/arm/mach-tegra/tegra3_speedo.c
arch/arm/mach-tegra/timer.c
arch/arm/mach-tegra/usb_phy.c
arch/arm/mach-tegra/wakeups-t3.c
drivers/cpufreq/cpufreq_interactive.c
drivers/input/touchscreen/atmel_mxt_ts.c
drivers/mfd/tps65090.c
drivers/mmc/core/mmc.c
drivers/mmc/host/sdhci-tegra.c
drivers/mmc/host/sdhci.c
drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c
drivers/regulator/Kconfig
drivers/regulator/core.c
drivers/regulator/tps80031-regulator.c
drivers/spi/Makefile
drivers/staging/nvec/nvec.c
drivers/tty/serial/Makefile
include/linux/mmc/card.h
sound/soc/tegra/tegra_max98095.c
sound/usb/card.c
Change-Id: I65043bc6ce9e97d0592683462215a39e50f403fd
Reviewed-on: http://git-master/r/121392
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: I00c67d6ec68c7566c2764aa8d135c101bacc17d7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Change-Id: Ia61054f13fee9bcefaa290364297bbaeaa725110
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
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Decrease the priority for 2D operations so they do not compete with display.
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/76683
(cherry picked from commit 2094d7c0b435b8a22c81a4bc5d54d4a697518f3a)
Change-Id: Id559a585a4826a370850c893fda21f47ab339019
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/79994
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Rebase-Id: Rf5b073de01845748b038e55922c7be299c73cc90
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Reviewed-on: http://git-master/r/76065
Change-Id: I8eb5148399cc8a08c2f37f20927b655f3e909241
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76817
Reviewed-by: Automatic_Commit_Validation_User
Rebase-Id: R0bb294468ebbc74fb13036c69134143c5c9d3323
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Requesting to set LA for zero bandwidth would otherwise
cause division by zero exception in LA computation. LA can
safely be set to max in this case.
Original-Change-Id: Id234e2432c7c21b7ab3d13614d0f9fbd82199cde
Reviewed-on: http://git-master/r/47132
Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com>
Tested-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R58676140d46d2b7b2b2c117a03f088944a8f4382
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arch/arm/mach-tegra/latency_allowance.c:499: warning: format '%4u'
expects type 'unsigned int', but argument 4 has type 'long unsigned int'
Original-Change-Id: Idfea3e60da375bfe903e1a517505c727ecc83d72
Reviewed-on: http://git-master/r/46495
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R8eeb5ccc518d9591fa1a9a521913b17ec28c6b52
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In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.
Bug 840688
Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1
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add /sys/kernel/debug/tegra_latency/la_info to print programmed latency
allowance settings.
Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77
Reviewed-on: http://git-master/r/42285
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09
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Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91
Reviewed-on: http://git-master/r/36570
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9
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