Age | Commit message (Collapse) | Author |
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Fix PCIe clock and reset not conforming to specification by moving PCIe
reset handling including the PLX PEX 8605 errata 5 workaround from the
board platform data into the right places timing wise in the PCIe driver
itself.
Also add a kernel command line argument to allow using the Apalis GPIO7
as a regular GPIO rather than for above mentioned PLX PEX 8605
workaround:
pex_perst=0
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.
Bug 1521306
Reviewed-on: http://git-master/r/225399
(cherry picked from commit df0760bf515236bed2e87e590509642ab72a01b5)
Change-Id: I7b44ea51e7e02f2bca93cfc75ed85e01ab91fe03
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
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Tegra20 and Tegra30 do not support gen2 PCIe, so correct the
register setting to disable it.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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The drivers internal root_bus_nr used to be u8 which lead to a wrong
error detection in bus_to_port. Bus number can be -1 in case bus is
not scanned yet. Thanks to James pointing that out.
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Avoid AXI response decoding errors of the following form by properly
setting the root bus number:
[ 3.377991] PCIE: AXI response decoding error, signature: ff01003d
[ 3.384174] PCIE: AXI response decoding error, signature: ff01003c
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Revert the following commit:
4bb48c289cdfddf02673b5b3dd1a735dfd5d972e
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Fix the following build error using our OpenEmbedded gcc-4.7:
arch/arm/mach-tegra/pcie.c:335:22: error: 'reg_pmc_base' defined but
not used [-Werror=unused-variable]
cc1: all warnings being treated as errors
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Add new PCIe driver fixing multi-port operation. Pulled from
Linux_Kernel-src_CARMA_DevKit-ver3.1.10_l4t_Rev545.tgz.
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Setting DFPCI_RSPPASSPW bit in AFI_CONFIGURATION
register to avoid instant hang on CPU read/write
while gpu transfers are in progress.
Bug 1034443
Change-Id: I40c99588753b8b2cb2d418b54c6ac73f7b8ddc13
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/124037
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Setting default values in TXBA registers to avoid
unfair arbitration between downstream reads and
completions to upstream reads
Bug 1027024
Change-Id: I87763817b7974127f93fa18270b5245a54fc6676
Signed-off-by: krishna kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/120359
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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1. Initialize PCIe on every resume whether device
is dock/undocked.
2. Poweroff PCIe if Poweron failed at any stage.
3. Make PCIe initialization robust so that it is
successful anytime dock is connected i.e while
in LP0 or after it's exit or else.
Bug 1020949
Change-Id: I79cd75f2bf7164a9b5c8906a370364dba5183ac8
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/117532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Rearranged the code to release all memory and res-
ources whenever poweroff is called and re-allocate
them whenever power on is called.
Bug 963969
Change-Id: I31d9cd1e8603e638714bba765aadfdd4eed78d93
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/116048
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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1. Removed the stop/add pci devices after rescan to
avoid panic in 2nd time suspend for L4T.
2. Moved the setting irq code before adding devices
to avoid probe failure for usb3.
Bug 959642
Bug 946385
Bug 1009086
Change-Id: Ia425a4e11667f6f2f110eb68d63c8fb229486c21
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/112959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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1. Remove unwanted macros and rename some of macros
and apis
2. Add comments for description of some statements
Bug 959642
Bug 956573
Change-Id: I8fa7df9317eb511a00346308ec6a219322e958af
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/107840
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Currently, only L0s state of ASPM is supported by default.
This change enables the l1 state support for Root Ports.
Bug 815499
Change-Id: Iec5e5f2edbf4ccfa35cb74432e18b29f18ec7771
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/110062
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jay Agarwal <jagarwal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
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Stop and add pcie devices to probe the devices
again in order to have correct value of irq which
was not, at first probe while resume.
Bug 956573
Change-Id: I8d497116350ad263c4ae3053cd429393a0f0bc99
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/110556
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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1. do power off on suspend and power on while
resume and other initialization.
2. call same functionality as suspend/resume
for disconnect/connect of hotplug also.
Bug 946385
Change-Id: Ic6906a8641f418cc3e5ee86beaf6fb3f71081174
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/110343
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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1. Do add port and rescan in resume
2. Assert pcie xclk on power on
3. Remove all bus and devices in suspend
4. Enable msi once after resume also
5. Remove Most of hacks for save and restore
config spaces
Bug 959642
Bug 956573
Change-Id: Ibfa6902ad1aa2ed0d97f7fe1e305287e38ea0be1
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/109700
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- Adding flag to treat warning as error.
- Handling warnings of unused variable, structures and functions,
wrong return type, wrong type comparision.
Bug 949219
Change-Id: I9d02387ce1073c4e46f69d01669285aa3754f1d9
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/104968
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 949219
Change-Id: I91a67d30869e9800c483f112d58b9f76e2dbe361
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/103534
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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PCIE dock detection is done using GPIO for cardhu
e1291 board. Currently supporting only hotplug
disconnect when all pcie devices will be stopped
and will not work on hotplug connect later.
Bug 912743
Bug 955043
Bug 946385
Change-Id: Ibb2869c12e193be5e6e7e057e149e7699598a061
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/87315
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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1. Restoring control register correctly.
2. Enabling clock clamping while resume
Bug 959642
Change-Id: Ic97306b4dfed0e131274aa93b35dba3f906e55be
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/103127
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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PCIE card on second port doesn't get detected if the first
port is empty. If the link for first port is reset and the
second port is queried for card, it doesn't get detected.
Fix for the issue is do not reset the link if the port is
not detected in third attempt.
bug 970206
Change-Id: I4e4d32c22697b817381834ac746417437016d7f3
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/101986
(cherry picked from commit c085f6b1b3a77b7aae3b04e22c7a9bfed8517c1e)
Reviewed-on: http://git-master/r/103077
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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Bug 984434
Change-Id: I7184fc77132485ab24357e5f2c965ddf4eca6a07
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/103112
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Its observed that PCIE all clocks enabled on resume.
Follow up resume and suspend only if any port added
bug 943712
Change-Id: I0644aad8a4994726451cda094f2607eb8398aadf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/95836
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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1. disable read write operation while suspend/resume
noirq operation is performed to avoid hang
2. implement dev pm_ops for pcie tegra driver
3. use a backup buffer to save config space of
all pcie devices to avoid legacy PM calls.
Change-Id: I2d39f69a865b48e1e51ce2cd466e24007718a8b6
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/90617
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Penny Chiu <pchiu@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Emily Jiang <ejiang@nvidia.com>
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1. disable pci devices asynchronous suspend/resume.
2. correct resume function of tegra pcie driver.
3. enable clock clamping
4. require noirq suspend/resume calls to be commented
Bug 790141
Bug 947673
Change-Id: I49ebba43f296c3c38bc960d7db5fe847232e29a8
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/87316
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Penny Chiu <pchiu@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
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Fix compilation error for PCIe.
Change-Id: I1ab5390dfce273236bd4aa09579bf54425faf2e9
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/90045
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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1. Removed mdelay in reset code since pci devices
are not detected with this.
2. Moved the reset logic down in retry label.
Bug 637871
Change-Id: Idd6344860e513407d5f8c8ba05e1beef0f39bf57
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/89128
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This commit fix two issues.
1. MMIO space should be reserved for T30 as well
2. There is a bug in link reset sequence causing
problem in detecting the other slot as well
on T20
bug 826956
bug 637871
Reviewed-on: http://git-master/r/66814
(cherry picked from commit 11ce98902d0687646eb30a4bd1f9a1d5e8da34ce)
Change-Id: I1843e3a1d897a36768b05b33ab7624889191d011
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/86134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
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All these clock operations should be handled by
powergate operations.
bug 840051
Reviewed-on: http://git-master/r/66177
(cherry picked from commit 1ad8fe3e184db04063275c837e240827bda009e9)
Change-Id: I0159c6c1f64932b22b25d31d4bb1ff9d41385879
Reviewed-on: http://git-master/r/86126
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Clear the interrupt status before posting events to driver code, to avoid
losing interrupts for devices with high interrupt rate.
Change-Id: I776dff33e273b7d1c0dd10615ce4405acdc867e8
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/84356
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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This patch fixes multiple port detection issue
in tegra pcie driver.
The issue is fixed by reserving IO resource
from ioport_resource memory and PCI MEM and
PCI PREFETCH MEM from iomem_resource. These
memory resources are common to all root
ports. The resource allocation is done in
preinit function.
MMIO space should be reserved for T30 as well.
fixes bug 637871
Signed-off-by: Manoj Chourasia<mchourasia@nvidia.com>
Change-Id: I555b90bd1e0033965c78772dbdc75ea8efd039dd
Reviewed-on: http://git-master/r/79800
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Jeremy Alves <jalves@nvidia.com>
Reviewed-by: Kaushik Sen <ksen@nvidia.com>
Tested-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Mike Thompson <mikthompson@nvidia.com>
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Section mismatch warning messages were due to declaring tegra_pcie_hw using
__initdata & tegra_pcie_scan_bus using __init.
Hence removed them.
bug 929358
Reviewed-on: http://git-master/r/76495
Change-Id: I1894c1c360e0fc0f3da18bbe840e88afa4de6ffc
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77308
Reviewed-by: Automatic_Commit_Validation_User
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replace virt_to_bus with virt_to_phys to avoid
compilation warning of obsolete identifier
Change-Id: I296fd2ee54ce71afd318f46aa9c9bec4e80dab0f
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/70635
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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Fixed issues in entering suspend mode when
no pcie devices are connected
bug 873836
bug 876954
bug 884808
Reviewed-on: http://git-master/r/51506
(cherry picked from commit ae3b130e0458731a04b6d961f84831da7a2ce711)
(cherry picked from commit 05697d94499eb94bf3e1ccd87c1382a4b10dec7e)
Change-Id: I2a0fd104d2443c84edea2d62debc242b497fc38d
Signed-off-by: Peer Chen <pchen@nvidia.com>
Reviewed-on: http://git-master/r/70636
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mursalin Akon <makon@nvidia.com>
Tested-by: Mursalin Akon <makon@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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Restate MSI irq desc in architecture specific
functions. This way, PCI device drivers can later
on hook those irqs.
Plus, a minor fix.
Change-Id: I3d9ba84c071309343b58c6200a9f53708e4043f4
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/70631
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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Fix the return value from MSI irq routine. Without this
change __report_bad_irq is invoked at MSI interrupt.
Bug 870667
(cherry picked from commit 30f82dda084d9260ed550585d16629872f703b0d)
Change-Id: I0f75d1a369c93f0f1e3203bdb1d875249a86337a
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/70630
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mike Thompson <mikthompson@nvidia.com>
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
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MSI style interrupt support is being added to
pcie driver
Fixes bug: 637871
Reviewed-on: http://git-master/r/47330
(cherry picked from commit de7fd8768b32da66eaf4eaf58473c65f7a76808d)
Change-Id: I105db7d08b545e75832f12433d8c2d233444294a
Signed-off-by: Krishna Kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/62066
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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Added support for tegra3 to pcie driver
Fixes bug: 637871
Reviewed-on: http://git-master/r/44989
(cherry picked from commit 9bbfb4189474ede7f16a20b564ac7da2a93f6750)
Change-Id: Ic0bb5b8d3098030baee5d8db6ca043df71db5a8e
Signed-off-by: Krishna Kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/62059
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
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This change provides a centralized location for powergating modules.
It would take care of switching on/off clocks while un-powergating/
powergating modules respectively.
Bug: 814267
Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710
Reviewed-on: http://git-master/r/31776
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
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git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: remove printks about disabled bridge windows
PCI: fold pci_calc_resource_flags() into decode_bar()
PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
PCI: correct pcie_set_readrq write size
PCI: pciehp: change wait time for valid configuration access
x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
PCI: ARI is a PCIe v2 feature
x86/PCI: quirks: Use pci_dev->revision
PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
PCI hotplug: cpqphp: use pci_dev->vendor
PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
x86/PCI: config space accessor functions should not ignore the segment argument
PCI: Assign values to 'pci_obff_signal_type' enumeration constants
x86/PCI: reduce severity of host bridge window conflict warnings
PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
PCI: PCIe AER: add aer_recover_queue
x86/PCI: select direct access mode for mmconfig option
PCI hotplug: Rename is_ejectable which also exists in dock.c
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Aside of the usual motivation for constification, this function has a
history of being abused a hook for interrupt and other fixups so I turned
this function const ages ago in the MIPS code but it should be done
treewide.
Due to function pointer passing in varous places a few other functions
had to be constified as well.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
To: Anton Vorontsov <avorontsov@mvista.com>
To: Chris Metcalf <cmetcalf@tilera.com>
To: Colin Cross <ccross@android.com>
Acked-by: "David S. Miller" <davem@davemloft.net>
To: Eric Miao <eric.y.miao@gmail.com>
To: Erik Gilling <konkers@android.com>
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
To: "H. Peter Anvin" <hpa@zytor.com>
To: Imre Kaloz <kaloz@openwrt.org>
To: Ingo Molnar <mingo@redhat.com>
To: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Krzysztof Halasa <khc@pm.waw.pl>
To: Lennert Buytenhek <kernel@wantstofly.org>
To: Matt Turner <mattst88@gmail.com>
To: Nicolas Pitre <nico@fluxnic.net>
To: Olof Johansson <olof@lixom.net>
Acked-by: Paul Mundt <lethal@linux-sh.org>
To: Richard Henderson <rth@twiddle.net>
To: Russell King <linux@arm.linux.org.uk>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-pci@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: sparclinux@vger.kernel.org
Cc: x86@kernel.org
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Convert PCIBIOS_MIN_IO and PCIBIOS_MIN_MEM to variables to allow
multi-platform builds. This also removes the requirement for a platform to
have a mach/hardware.h.
The default values for i/o and mem are 0x1000 and 0x01000000, respectively.
Per Arnd Bergmann, other values are likely to be incorrect, but this commit
does not try to address that issue.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Colin Cross <ccross@android.com>
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Move tegra_pcie_power_off before tegra_pcie_power_on for clean addition
of PCIE power gating
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Colin Cross <ccross@android.com>
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Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: Arnd Bergmann <arnd@arndb.de>
CC: Russell King <linux@arm.linux.org.uk>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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