| Age | Commit message (Collapse) | Author |
|---|
|
There was typo bug in the gpio-pingroup table where gpio M6
is configured for LD1 pingroup.
Correcting table entry to configure GPIO M6 to pingroup LDI.
Change-Id: I6938e3e7b28525a920c8a8c6eb59d7013c1f97d0
Reviewed-on: http://git-master/r/8182
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Martin Chi <mchi@nvidia.com>
Tested-by: Martin Chi <mchi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Pad control register should be saved before LP0
and restored after LP0.
(cherry picked from commit df7e8107f49e15d5652b63b5a3d35121b9f722ad)
Change-Id: I8679de6bccf6292a41a79b5603a9f02da41f8b15
Reviewed-on: http://git-master.nvidia.com/r/5333
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
|
|
To avoid spurious signal transitions on exit from deepsleep
pinmux restoration should be done in an order.
Change-Id: Ie7fc48c964aef83d7f6c5e150d9b0f387bd26998
Reviewed-on: http://git-master/r/4116
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
|
|
Change-Id: I9bb3607e9605eefd5c0eec07a8be3fafce9bae64
Reviewed-on: http://git-master/r/2528
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
|
|
tegra 2 platforms are designed using a table of standard pinmux
configurations for each muxed interface
Change-Id: I125ae4a9dde7283bab2ec20a5abb3a2b8aaea964
|
|
ensure that the pad group containing a requested GPIO is not in tristate
before clients use it.
add a tegra 2-specific table to map from the GPIO number to the pad group
which contains it
Change-Id: Iab930ac0df27735190d5b1eca5becb5e584d99d6
|
