summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/pinmux-t2-tables.c
AgeCommit message (Collapse)Author
2012-05-14ARM: tegra: Correction of safe optionAshwini Ghuge
Corrected safe option for LPW0 and LPW2 Bug 920686 Change-Id: I14e1a22de3338ba569d3b381508e123d12aad059 Reviewed-on: http://git-master/r/101973 Tested-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-30arm: tegra: pinmux: correct pinmux setting for DDC and PTA groupSanjay Singh Rawat
The safe function setting is not correct for the pingroup Bug 901383 Change-Id: I5a7340b0d4951d844e3b1824edbfc6de4fec0006 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/64371 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb9e9261e3725f21bcb97edaf71d16f7c0aed2eaa
2011-11-30arm: tegra: pinmux: Clean up table formattingScott Williams
Clean up the formatting of the pinmux tables to make them readable again. Change-Id: I8640e8bdb6c584e6f69f2d3b8e0a9bc040a7e3ee Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/63019 Reviewed-by: Stephen Warren <swarren@nvidia.com> Rebase-Id: Rd962753a864f55556a7600ca7b1fd78fc24cb440
2011-11-30Arm: Tegra: Cardhu: Set slew rise/fall rates properlyPavan Kunapuli
Setting the slewrise and slewfall rates properly. Bug 811303 Reviewed-on: http://git-master/r/52367 (cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031) Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836 Reviewed-on: http://git-master/r/62326 (cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9) Reviewed-on: http://git-master/r/63813 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
2011-11-30ARM: tegra: gpio: Set a gpio to tristate or normalChaitanya Bandi
Create mapping from gpio to pingroup and set gpio to normal or tristate Bug 866633 Reviewed-on: http://git-master/r/56557 (cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115) Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21 Reviewed-on: http://git-master/r/61120 Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e
2011-11-30ARM: Tegra: Pinmux: Fix drive strength configurationPavan Kunapuli
In T30, different pad ctrl group registers have different pull up and pull down drive strength field offsets and maximum values. Modified drive_strength structure to be able to pass the offsets and masks of each group to ensure that drive strengths are properly configured. Bug 870369 Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704 Reviewed-on: http://git-master/r/49872 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd
2011-11-30ARM: tegra: Fix modpost warningScott Williams
Change-Id: I69f9b9f74a98ef31f496478e48896dc51044a72e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49273 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf384c1b08e441df3a7aeb4bba86a78da1663a7d2
2011-11-30arm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD valuesMayuresh Kulkarni
The pin-func set by board-xxx-pinmux.c should be one of the 4 possible values of the pin-func in master pinmux table. Also the safe pin-func setting should follow the same rule. If this is not followed then, warnings will be seen whenever a driver tries to set a pin-func that is not in the master pinmux table. This is specically seen for the mux values RSVD_X. The hardware is always programmed with the bit value of setting (00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table. For bug 865503 Change-Id: I3933ca0002e099376798cc131690922fefa16868 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/48197 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9177fb046ede6bd39b98904d25a18622b72d4ce6
2011-11-30arm: tegra3: Keep DAP2 in maximum driver strengthLaxman Dewangan
Setting maximum driver strength of DAP2 in all tegra3 based system by default. bug 820361 Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a Reviewed-on: http://git-master/r/44497 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321
2011-11-30ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PMScott Williams
For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration parameter to use on Tegra for power management, and not CONFIG_PM. CONFIG_PM does not have the required dependency on CONFIG_SUSPEND necessary to pull in the CPU suspend/resume functionality used by Tegra. Also fixes compilation errors when CONFIG_PM and by implication CONFIG_PM_SLEEP are not configured. Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad Reviewed-on: http://git-master/r/40458 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
2011-11-30ARM: tegra: Update Tegra3 pinmux with syscoreDan Willemsen
Rebase-Id: R00882a09ec05783d83aa4b94b23458fddff9e7aa
2011-11-30arm: tegra: pinmux: Supporting LOCK/OD/IORESET pin configuration.Laxman Dewangan
Supporting the LOCK, OpenDrain (OD), IO_RESET configuration on pinmux register through pinmux apis. Original-Change-Id: I2459723c5fbcadd925331696c9469f64d2ba3b20 Reviewed-on: http://git-master/r/17532 Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Original-Change-Id: Ibd06c9a650ffbacf51530514e58bd52d1f60b4f2 Rebase-Id: R8e593a0b1e27db641d2e0c7b57a2946d97819f25
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: pinmux: Convert suspend/resume to syscoreColin Cross
Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I3228600e93f819821b13b0955961fc1cbfb826a8
2011-11-30ARM: tegra: remove unused mach/suspend.hColin Cross
mach/suspend.h is not used yet, and its functions will be replaced with syscore ops. Delete it. Change-Id: I7b32d3514e7f4427c7d5faa97c1954a7a2cc286c Signed-off-by: Colin Cross <ccross@android.com>
2011-02-09ARM: tegra: pinmux: Add missing drive pingroups and fix suspendGary King
Adds missing drive pingroups, saves all drive pingroups in suspend, and restores the pinmux registers in the proper order. Signed-off-by: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
2011-02-09ARM: tegra: Add prototypes for subsystem suspend functionsColin Cross
Signed-off-by: Colin Cross <ccross@android.com>
2010-10-21[ARM] tegra: pinmux: add safe values, move tegra2, add suspendColin Cross
- the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral - also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control - add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups) - move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code - fix debug output for group with no pullups - add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks. Signed-off-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-25 17:38:50 +0000