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path: root/arch/arm/mach-tegra/pinmux-t3-tables.c
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2012-08-08ARM: tegra: e1853: Update pinmux table entriesAshwin Joshi
Some of the entries in pinmux table are incorrect. Updated the table with correct entries. Bug 966833 Bug 1018258 Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com> Change-Id: I7ca486246fd51d83e865a9ef825be33011404a89 Reviewed-on: http://git-master/r/118282 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Ashwin Joshi <asjoshi@nvidia.com> Reviewed-by: Bhavesh Parekh <bparekh@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com> (cherry picked from commit a1aef89788f8660e7579a8ad555f1ef68d4c553b) Reviewed-on: http://git-master/r/119651 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-05ARM: Tegra: p1852: changed pinmux settingsMohit Kataria
Pinmux updated as per the latest pinmux sheet. Bug 978870 Change-Id: I122439df3d043216f1c8c2c1a0a3c88e74d760ee Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/111573 (cherry picked from commit 4e65d7d21b5ac5b25e3563ce6a7eb50cf1d8128d) Reviewed-on: http://git-master/r/103340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-06-01ARM: Tegra: changed pingroupsMohit Kataria
Changed pingroups with proper bit fields provided in TRM. Bug 978870 Change-Id: Ie02ff14448103c70e27149ac95cd487d33ab52c0 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/103353 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-05-04arm: tegra: Implement safe option for T30 pinmuxAshwini Ghuge
Bug 950086 Change-Id: I2eb129566bfea83b9a73d29f0c6443bdab087b65 Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/95518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Andy Park <andyp@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-02-23ARM: tegra: cardhu: set dap1 drive strengthNikesh Oswal
Change-Id: I1b3797b021adadd1ad944ede45b5916500a881e6 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/84542 Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-01-10Tegra: Pinmux: Fixed up errors about DTV interfaceAdam Jiang
Pin configuration on DTV interface could be enabled by this patch. Fixed Bug 904626 Fixed Bug 881303 Change-Id: I6b5dc12629740bb8275156df9d9a5b4ca9dae352 Signed-off-by: Adam Jiang <chaoj@nvidia.com> Reviewed-on: http://git-master/r/66626 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> (cherry picked from commit c34733e5ea933b322cd5edbceb93f921ffe413de) Reviewed-on: http://git-master/r/73955 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2011-11-30arm: tegra: pinmux: Clean up table formattingScott Williams
Clean up the formatting of the pinmux tables to make them readable again. Change-Id: I8640e8bdb6c584e6f69f2d3b8e0a9bc040a7e3ee Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/63019 Reviewed-by: Stephen Warren <swarren@nvidia.com> Rebase-Id: Rd962753a864f55556a7600ca7b1fd78fc24cb440
2011-11-30Arm: Tegra: Cardhu: Set slew rise/fall rates properlyPavan Kunapuli
Setting the slewrise and slewfall rates properly. Bug 811303 Reviewed-on: http://git-master/r/52367 (cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031) Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836 Reviewed-on: http://git-master/r/62326 (cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9) Reviewed-on: http://git-master/r/63813 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e
2011-11-30ARM: tegra: gpio: Set a gpio to tristate or normalChaitanya Bandi
Create mapping from gpio to pingroup and set gpio to normal or tristate Bug 866633 Reviewed-on: http://git-master/r/56557 (cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115) Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21 Reviewed-on: http://git-master/r/61120 Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e
2011-11-30ARM: tegra: Update copyrightsScott Williams
Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/51157 Rebase-Id: R795bf03590a76b6c494afd37603ed951dc2cd082
2011-11-30ARM: Tegra: Pinmux: Fix drive strength configurationPavan Kunapuli
In T30, different pad ctrl group registers have different pull up and pull down drive strength field offsets and maximum values. Modified drive_strength structure to be able to pass the offsets and masks of each group to ensure that drive strengths are properly configured. Bug 870369 Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704 Reviewed-on: http://git-master/r/49872 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd
2011-11-30ARM: tegra: Fix modpost warningScott Williams
Change-Id: I69f9b9f74a98ef31f496478e48896dc51044a72e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49273 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf384c1b08e441df3a7aeb4bba86a78da1663a7d2
2011-11-30arm: tegra3: Keep DAP2 in maximum driver strengthLaxman Dewangan
Setting maximum driver strength of DAP2 in all tegra3 based system by default. bug 820361 Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a Reviewed-on: http://git-master/r/44497 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321
2011-11-30arm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLKHarry Hong
SFIO3 on VI_MCLK pin is needed to output vi_sensor clk. bug 839517 Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb Reviewed-on: http://git-master/r/37426 Tested-by: Harry Hong <hhong@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b
2011-11-30ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PMScott Williams
For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration parameter to use on Tegra for power management, and not CONFIG_PM. CONFIG_PM does not have the required dependency on CONFIG_SUSPEND necessary to pull in the CPU suspend/resume functionality used by Tegra. Also fixes compilation errors when CONFIG_PM and by implication CONFIG_PM_SLEEP are not configured. Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad Reviewed-on: http://git-master/r/40458 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
2011-11-30ARM: tegra: Update Tegra3 pinmux with syscoreDan Willemsen
Rebase-Id: R00882a09ec05783d83aa4b94b23458fddff9e7aa
2011-11-30arm: tegra3: pinmux: Removing HDMI option from LCD_SCK/PWR0Laxman Dewangan
Removing the HDMI pinmux from pingroups LCD_SCK and LCD_PWR0 as per TRM document. Original-Change-Id: I85e3a5fb3af1cecbe6eb83d47e811362cd4ee629 Reviewed-on: http://git-master/r/29970 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R234087efc73a739d0fb50dc32fe31d74a12b40d0
2011-11-30arm: tegra3: pinmux: Adding SFIO2 option for CAM_MCLKLaxman Dewangan
Adding SFIO2 option as VI_ALT2 for the CAM_MCLK pin group. bug 821540 Original-Change-Id: Ic3fd6effd1ac2767c416f97491278f77bddbce76 Reviewed-on: http://git-master/r/29925 Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com> Reviewed-by: Abhiruchi Birajdar <abirajdar@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Danielle Sun <dsun@nvidia.com> Tested-by: Danielle Sun <dsun@nvidia.com> Rebase-Id: R32315427d3bd4bbab577363ec010be935225978b
2011-11-30arm: tegra3: Updating pinmux table based on TRMLaxman Dewangan
On tegra3 TRM, some of the pin mux option for a given pin group is not recommended and so not exposed in the TRM reference table. Updating the pinmux table accordingly. The non-recommended pin option is set as TEGRA_MUX_INVALID. bug 817099 Original-Change-Id: I572ee84912fe065a73e59d4f9ba0ce01223ead85 Reviewed-on: http://git-master/r/29626 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R88ad8a84c4516c8692b9266d6c073f20e35b420e
2011-11-30arm: tegra: pinmux: Supporting LOCK/OD/IORESET pin configuration.Laxman Dewangan
Supporting the LOCK, OpenDrain (OD), IO_RESET configuration on pinmux register through pinmux apis. Original-Change-Id: I2459723c5fbcadd925331696c9469f64d2ba3b20 Reviewed-on: http://git-master/r/17532 Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Original-Change-Id: Ibd06c9a650ffbacf51530514e58bd52d1f60b4f2 Rebase-Id: R8e593a0b1e27db641d2e0c7b57a2946d97819f25
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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