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Setting maximum driver strength of DAP2 in all tegra3
based system by default.
bug 820361
Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a
Reviewed-on: http://git-master/r/44497
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321
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SFIO3 on VI_MCLK pin is needed to output vi_sensor clk.
bug 839517
Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb
Reviewed-on: http://git-master/r/37426
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b
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For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration
parameter to use on Tegra for power management, and not CONFIG_PM.
CONFIG_PM does not have the required dependency on CONFIG_SUSPEND
necessary to pull in the CPU suspend/resume functionality used by
Tegra.
Also fixes compilation errors when CONFIG_PM and by implication
CONFIG_PM_SLEEP are not configured.
Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad
Reviewed-on: http://git-master/r/40458
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
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Rebase-Id: R00882a09ec05783d83aa4b94b23458fddff9e7aa
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Removing the HDMI pinmux from pingroups LCD_SCK and LCD_PWR0
as per TRM document.
Original-Change-Id: I85e3a5fb3af1cecbe6eb83d47e811362cd4ee629
Reviewed-on: http://git-master/r/29970
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R234087efc73a739d0fb50dc32fe31d74a12b40d0
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Adding SFIO2 option as VI_ALT2 for the CAM_MCLK pin group.
bug 821540
Original-Change-Id: Ic3fd6effd1ac2767c416f97491278f77bddbce76
Reviewed-on: http://git-master/r/29925
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Abhiruchi Birajdar <abirajdar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Danielle Sun <dsun@nvidia.com>
Tested-by: Danielle Sun <dsun@nvidia.com>
Rebase-Id: R32315427d3bd4bbab577363ec010be935225978b
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On tegra3 TRM, some of the pin mux option for a given
pin group is not recommended and so not exposed in the
TRM reference table.
Updating the pinmux table accordingly. The non-recommended
pin option is set as TEGRA_MUX_INVALID.
bug 817099
Original-Change-Id: I572ee84912fe065a73e59d4f9ba0ce01223ead85
Reviewed-on: http://git-master/r/29626
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R88ad8a84c4516c8692b9266d6c073f20e35b420e
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Supporting the LOCK, OpenDrain (OD), IO_RESET configuration on pinmux register
through pinmux apis.
Original-Change-Id: I2459723c5fbcadd925331696c9469f64d2ba3b20
Reviewed-on: http://git-master/r/17532
Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: Ibd06c9a650ffbacf51530514e58bd52d1f60b4f2
Rebase-Id: R8e593a0b1e27db641d2e0c7b57a2946d97819f25
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Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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