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path: root/arch/arm/mach-tegra/platsmp.c
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2015-01-20FIQ: Implement WDT FIQ debuggerRenn Wu
Implement Tegra WDT FIQ debug function. Default is disabled. Bug 1581432 Change-Id: Ic81ab4cd3285080016b37191e6e0fab18e330a30 Signed-off-by: Renn Wu <rewu@nvidia.com> Reviewed-on: http://git-master/r/#/c/271988 Reviewed-on: http://git-master/r/662550 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-03-27ARM: tegra: power: Add read fences in power gatingAlex Frid
To assure post of the previous writes through Tegra interconnect added read fences in the following power gating code paths: - Seconadry CPU boot ungating (path taken on Tegra11, Tegra14, Tegra12) - GPU rail clamps gating/ungating (path taken on Tegra12, Tegra13) - MC client ungating flush done (path taken on all platforms) Bug 1484343 Change-Id: Ie09ef37135beae0ed0beb1cd4d7e96187ba9be26 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/385403 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-03-07arm: tegra: initialize cpu reset handler using early_initcall()Varun Wadekar
tegra_cpu_reset_handler_init() was called during SMP prepare explicitly. In order to use PSCI calls during cpu reset handler init, it needs to be initialized using early_initcall(). The ARM init code makes sure that all early_initcalls are invoked before SMP is enabled. Cleanup the ARM64 version as well. Bug 1475528 Change-Id: I24d424b1c2ade4d5737764d6c5378b57ed3f8c7b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/378351 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
2014-01-21ARM: tegra: port inline assemblies for ARM64Peng Du
Port the inline assemblies w.r.t ARMv8 ISA and #ifdef the code with CONFIG_ARM64. Change-Id: I430b441cc23c88ef947ddb7c5aa1836d06dbabf9 Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/196609 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
2013-12-20arm: tegra: platsmp: setup fiq_glue for secondary CPUsVarun Wadekar
This allows us to get the callstack from the FIQ debugger, in case any secondary CPUs hangs. Bug 1326082 Change-Id: I7bbaf7226766764b88496a0a46d40b15fbc710a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/338252
2013-11-05fuse: cleanup unwanted fuse related dataShardar Shariff Md
cleanup of unwanted fuse related data as a part of migration of fuse driver Bug 1380004 Change-Id: I78ff9f6b1d3a27ae0ba0369ad9692c40e9e24bfd Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/310037 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-10-21arm: tegra: fuse: replace globals with functionsShardar Shariff Md
Replace globals tegra_sku_id, tegra_chip_id & tegra_bct_strapping with below functions u32 tegra_get_sku_id(void); u32 tegra_get_chip_id(void); u32 tegra_get_bct_strapping(void); Bug 1380004 Change-Id: I43eb2523e4af5d06bc1aa1f03c02c5168577878c Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/300401 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-10-17ARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}Ajay Nandakumar
Moving mach-tegra/clock.h and mach-tegra/timer.h to include/linux/tegra-cpuidle.h and include/linux/tegra-timer.h so that it helps faclitate the movement of drivers from mach-tegra/ to drivers/. Bug 1379817 Change-Id: Ia0a33c3f726d2f672409c270ac8ca1629f05eff8 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/299019 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra: Move mach/powergate.h to linux/tegra-powergate.hDan Willemsen
This moved upstream, do the equivalent change here. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I2de76e5c6487ed4513b6d070e0c515a27a881fff
2013-09-14ARM: tegra: Use <linux/clk/tegra.h> instead of <mach/clk.h>Dan Willemsen
So that the upstream common clk infrastructure can live side by side. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I0fe0ef8cd207d27b707821eed838c75b8ec04025
2013-09-14ARM: tegra: cputimer: reset IRQ affinity during cpu_disableSeshendra Gadagottu
(Original patch written by Paul Walmsley <pwalmsley@nvidia.com>) Switch the CPU affinity of the Tegra cputimer IRQ to CPU0 much later in the hot-unplug process - after sched_cpu_inactive() runs. The code originally added by commit 6012d7167f715f91a43f0bf826aae00de0e5f860 ("ARM: tegra: fix warning related to soc timer irq affinity") switched the CPU affinity of the Tegra cputimer IRQ during the CPU_DOWN_DISABLE phase of the cpu_notifier. This is the same phase used by sched_cpu_inactive() to mark the CPU as unavailable to the scheduler, as well as by cpufreq_cpu_callback(). The call to sched_cpu_inactive() must take place before the CPU affinity of the cputimer IRQ is reset. Unfortunately there's no easy and clean way to enforce ordering inside this notifier chain. This could result in the following attempted notifier callback sequence: 1. Tegra cputimer hotplug_notify() -> CPU1 no longer receives scheduler ticks from its local timer 2. cpufreq_cpu_callback() -> eventually winds up in schedule() - but cannot make progress because the scheduler tick is never received -> HANG 3. sched_cpu_inactive() To work correctly, the CPU affinity of the Tegra cputimer IRQ must only be switched after sched_cpu_inactive() runs. The initial approach attempted was to move the affinity switch to the CPU_DYING cpu_notifier event. This causes warnings to be logged to the kernel console by the ARM migrate_irqs() code, which does not expect an IRQ to have an affinity to a downed CPU. So instead, we move the affinity switch to the Tegra-specific callback for the cpu_disable() smp_ops function pointer. This is called between the CPU_DOWN and CPU_DYING cpu_notifier events. Bug 1309706 Bug 1317133 Change-Id: I2756843917c77ac1405c35bd726a7294f947e406 [sgadagottu@nvidia.com: removed EXPERIMENTAL notations; removed Cc: lines; wrapped references to tegra_cputimer_reset_irq_affinity() in #ifdefs; updated copyrights] Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/243683 (cherry picked from commit dbd37f36c6793377e59a9d69a12542fd32ca224f) Reviewed-on: http://git-master/r/247335 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: Tegra: smp: Check chipid before dual core SKUGraziano Misuraca
Change-Id: Ia622e439d385ad2affb0958f9c86fccd3eef71a6 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-on: http://git-master/r/249910 (cherry picked from commit 00da56084285e681be834b08f3c6f0921a31612f) Reviewed-on: http://git-master/r/250819 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2013-09-14ARM: Tegra: smp: case to setup_core_count for T40DCGraziano Misuraca
T40DC (dual core) SKU will not have FUSE_SKU_DIRECT_CONFIG_0 set so we need to check the SKU explicitly and set the number of cores to two in that case. Bug 1262581 Change-Id: I341a606698a5bd72374adaecdcbaf3ef62e351d3 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-on: http://git-master/r/234210 (cherry picked from commit 4402ec2394f686e90453b881eaa162db95b303bc) Reviewed-on: http://git-master/r/240684 (cherry picked from commit e06aea34a825185de5ee479009da2c970f1133c1) Reviewed-on: http://git-master/r/249748 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2013-09-14arm: tegra: ardbeg: add initial board fileMitch Luban
Adding basic board file for ardbeg. Bug 1257423 Change-Id: I6c8c666da189e6b0ea39024218937ded2f8fe148 Signed-off-by: Mitch Luban <mluban@nvidia.com> Reviewed-on: http://git-master/r/216248 Reviewed-by: Chao Xu <cxu@nvidia.com>
2013-09-14ARM: tegra: remove duplicate defines for chip_idMayuresh Kulkarni
- the chip id have been defined in 2 places: fuse.h as TEGRAXX & mach/hardware.h as TEGRA_CHIPID_TEGRAXX - some part of code used defines from fuse.h while others used mach/hardware.h - this commit removes the defines in fuse.h and converts all the code to use the defines from mach/hardware.h - kernel in dev-chips is also using defines from mach/hardware.h Change-Id: Ia65f8ead3f8eccdd6cba4a159c3d0e16a2566e41 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/208375 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14ARM: tegra14x: Add routines to maintain powermasksPrashant Malani
The decision to enter LP1BB might occur well into iRAM code. These functions will help to save and restore cpu_power_mask in case we decide to enter LP1BB in iRAM. Bug 1236920 Change-Id: Ic1e38281bdc508014d4edb3e9645c7ba89a2b4c1 Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/203166 (cherry picked from commit 8fc48afefb64fecb99db1d2cab1ac57d0af19bb2) Reviewed-on: http://git-master/r/204858 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-09-14ARM: tegra14x: secondary cpu booting sequenceSeshendra Gadagottu
Secondary cpu boot sequence corrected for first time booting and hot-plug booting. For first time booting partition power un-gating needs to be done. For hot-plug booting flow controller needs to be programmed for SCLK event trigger. Also fixed the merge issue in tegar11 code, so that tegra11 hotplug code can be re-used. Change-Id: I65673fb221b47eb24169d8c8cd7a8ebb1db5dd15 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/174363 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra11x: CPU1-3 start up fixChandler Zhang
The first time when a CPU powers up in kernel, it has to be done by directly toggling PMC register. Remove the flowctrl_write_cpu_halt() call. Bug 1191165 Change-Id: I22cabf0a10ae24af568ac317b241cefb8ba59fae Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/170970 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2013-09-14ARM: tegra14x: hot-plug for secondary cpu'sSeshendra Gadagottu
T14x flow controller logic is same as T11x, but PMC_CLAMPING logic is same as T30. To take care of these conditions separate sequence for booting of secondary cpu's for T14x is added. Change-Id: I7a6776b48ae7c79574ae81c09aafc4961c86fbfd Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/163131 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14DROP: merge errorDan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2013-09-14ARM: tegra14x: Powering up secondary CPUsSeshendra Gadagottu
Change-Id: I8af4f7869054b4a835ef5c7ee14d5fbcef89f0b6 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/118440 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra11: power: Update core EDP on CPU cluster switchAlex Frid
Update core EDP limits when CPU cluster is switched between fast (G-mode) CPU, and slow (LP-mode) CPU. Bug 1165638 Change-Id: I956eb5ab2d8fbe873f998cca1e22984413cf5743 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/165617 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra11x: Simplify cpu hotplug sequenceBo Yan
There is no need to clear CPU CSR register. The "ENABLE" bit (bit 0) is set by software, but cleared by hardware once the sequence is completed. In case of failure, it's desirable not to change it for debug purpose. After CPU_CSR clear is removed, the power mask is set by the CPU that's booting up. Change-Id: I4879c64ec5858ed85008fbeeedb8232e35643a8c Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/164891 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2013-09-14ARM: tegra11x: Fix race condition in cpu hot plugBo Yan
The secondary CPU power up can happen so fast that it enters power gating even before the CPU that's trying to bring it up gets a chance to check status in PMC register. This can happen because interrupt and preemption are not disabled, so the primary CPU can switch to do something else, when it comes back to check PMC status, it's already too late. When this happens, it will simply declare a timeout failure, though the secondary power up is actually successful. The fix is to check online status as well, because the CPU that's coming up will set online flag before entering idle loop. Another enhancement is to skip the status check altogether if this is not the first boot up after cold boot or warm boot. The synchronisation done in __cpu_up is more adequate. For the first boot after cold boot or warm boot, set the timeout back to 100ms. Bug 1169512 Change-Id: Ie4b873d853c40207c7b1bc1acf0982a7bf0ecd9f Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/164065 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
2013-09-14ARM: tegra11x: increase wait time for core power upSang-Hun Lee
tegra11x is taking 2 seconds for core power up currently Increase the wait time to avoid a failure Bug 1169512 Change-Id: Ie5b2c35bc846ece47920f99be3b369b9ede73e0f Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/162527 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2013-09-14ARM: tegra: make wait time proportional to HZSang-Hun Lee
The current implementation waits a constant number of jiffies, which would give the system less time for a core boot up if we increase HZ Bug 1169512 Change-Id: I789feaa7c3d528b99d2d1b9163bd5394957c626e Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/162480 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2013-09-14ARM: tegra11x: CPUID virtualization supportBo Yan
This is the first patch to support CPUID virtualization. The goal is to treat all CPUs as equal in software. In current implementation, CPU0 is the anchor CPU, which must be the first one brought up, and the last one taken down. This patch removes that restriction. the cluster switch still has to start from CPU0 with this patch. This can not coexist with secure OS Reviewed-on: http://git-master/r/144610 (cherry picked from commit d32fba4be39e3f9a95ef5ab44d0c64dc6d2808a3) Change-Id: Ib7fcaae751d17fee839a4f228f5ef5c3ee2390c2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/159486 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R09e29d45acf92b3ad2d909d5438c3375aa85e7dd
2013-09-14ARM: tegra11x: CPU start up fixBo Yan
The first time when a CPU powers up in kernel, it has to be done by directly toggling PMC register. Subsequent CPU power up sequence is controlled by flow controller. This is done after LP0 exit as well. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/143296 Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146484 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R8909dae486432fd628e8d89735634eee26063f4e
2013-09-14ARM: tegra11x: Fix the secondary CPU start upBo Yan
The secondary CPU startup sequence of t11x is different because flow controller behavior has changed, so fix it accordingly Change-Id: I26aa26593943fde0cf7b599b4fca04644715ca4a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/138705 (cherry picked from commit 79ecf6b4ba3902b1b5bd79d8d4942884a8dc78eb) Reviewed-on: http://git-master/r/143973 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R1fbf3fe1f0c175f930ed452cdf2d3758eaa392c2
2013-09-14Revert "arm: tegra: Enable speculative line fill in SCU."Krishna Reddy
This reverts commit 06c880a6086183173c361b4a9d4f8047c6a39769. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I7ff9ffbfe74e2083aa43cab75b694b1c61987bc3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/125097 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Rebase-Id: Rc0198bdf02ba5b692efd503e0bd25fc52e6bd2b3
2013-09-14Revert "arm: tegra: scu: Enable IC and SCU standby"Krishna Reddy
This reverts commit b25193d5c3e2c59169c127d23b59123136cfefa7. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I9858c88a6e846d2c3629f14c7cc62a7feb4f4528 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/125096 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Rebase-Id: R28f527b5db038bb6d79b60717be50af6f0ca2dac
2013-09-14ARM: tegra: fix section mismatch for get_core_countPeter De Schrijver
get_core_count calls scu_get_core_count which is part of the __init section. Hence we can only call this from another function inside this section. Refactor the code to initialize number_of_cores at boottime in an __init function. Change-Id: I200a6ea297a8abe1a3b3fbdd050de5917875d7bc Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/117053 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Ra89316289b1c471916dcbc9e3b260894b2f34265
2013-09-14ARM: tegra: power: Enforce CPU rate range in secondary bootAlex Frid
On Tegra3 make sure cpu rate is within G-mode range before LP to G mode switch triggered by secondary cpu boot directly from LP mode. Bug 988544 Change-Id: I0d86fbf0727a6bbf6069159e7c532947a9d0af73 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115930 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Greg Lo <glo@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R2058bc1820b2d27c927de4b2d5b2bc03746fd668
2013-09-14ARM: tegra11x: Powering up secondary CPUsBo Yan
Change-Id: I30e115061c24f1a8f3f11cab0f21678d3cf096f1 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/113766 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Rbdcccb2d66aac3e30cc452766d287fc562bfd89f
2013-09-14ARM: tegra: Switch off inlining get_core_countAmit Kamath
bug 949932 get_core_count function was optimized for only case of T20. Since the available_cpus function has got conditional compilation. This resulted in execution of mrc instruction to cop which is meant for A15 arm core. Change-Id: Ia9c0f284362adaf61fa18fe05370954666a283bc Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/95569 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Rebase-Id: R212658bcf5a45e44ffec2a182ab9074a01d0af74
2013-09-14ARM: tegra: Fix CPU core count detectionScott Williams
The detection of the number of CPU cores when no SCU is present was incorrect and would result in a kernel panic. Correctly determine the CPU type first and then use the proper method for obtaining the CPU count. Change-Id: I9570e2f0b7443576a754dfd49d6fb46236c9cf47 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/92930 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Ra691be09f25cf2eaa65b9f2878e974bed087478f
2013-09-14arm: tegra: convert logical CPU numbers to physical numbersPrashant Gaikwad
Bug 941810 Change-Id: I0ed732a35dff4884c74ee3c0bf38fb3c3e5c9efc Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/87181 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rc1acb149dbc53402f300fd9867dc283081e089f4
2013-09-14ARM: tegra: smp: Add support for Cortex-A15 boot_secondaryScott Williams
Cortex-A15 does not have a memory-mapped SCU in the PERIPHBASE aperture. Instead, the number of CPUs present is obtained from the architectural L2 Cache Control (L2CTLR) register. Enable HAVE_ARM_SCU only on platforms that have a memory-mapped SCU and add the necessary conditionals to prevent access to the memory-mapped SCU address range on platforms that don't. Change-Id: I4027d034fe79339fab0030a44780240785206cba Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/79341 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Jeff Smith <jsmith@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Rebase-Id: R62dcd56e7abed8ef5cef60325c6ca52fbfb43b22
2013-09-14unknown changes from android-tegra-nv-3.4Dan Willemsen
Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
2013-09-14fixup: remove unused code from platsmp.cDan Willemsen
Rebase-Id: Ra1789ff842b792d442d5c11266dedbde07af8589
2013-09-14arm: tegra: scu: Enable IC and SCU standbyKrishna Reddy
Bug 947861 Change-Id: I1ac97b5de5e7e79a418b3c38c70df4976616cdf3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/100457 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R7d702046b68e7e2e5ee36f1ceca5779ac5cd982d
2013-09-14arm: tegra: Enable speculative line fill in SCU.Krishna Reddy
Enable speculative line fill in SCU. Bug 947861 Change-Id: I2db7515c47715160a4e559931e178b41c01a1744 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/91834 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Ra417206fd2895f95226617212dc7dfb088af8c88
2013-09-14ARM: tegra: reduce LP0 resume CPU power on timeJin Qian
cherry-picked from adf08ef4030598a6bf9036f45584be8acc008fea Bug 862504 Change-Id: I79460aa4abdccc4f2ca17867197bb12668d59dea Reviewed-on: http://git-master/r/52420 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rffc2d7314a61f04274e0db116c5a1cb7004dc77d
2013-09-14ARM: tegra: Update copyrightsScott Williams
Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/51157 Rebase-Id: R5aa782b116daefeb126b3bf58af90a7fd78f648d
2013-09-14ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster controlScott Williams
Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48798 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f
2013-09-14ARM: tegra: Avoid timer calibration on slave cpu's.Krishna Reddy
Use the value calibrated by master cpu. Bug 843553 Original-Change-Id: I88939f37050873e0633782f6a927ffaf9b8d776d Reviewed-on: http://git-master/r/47988 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6520764a88346d5ab4a180810636b04ce474f4d7
2013-09-14ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re0c233ed4bacc27feb7b210cddc6ff3e487c528f
2013-09-14ARM: tegra: Handle uniprocessor all CPUs booted statusScott Williams
For CONFIG_SMP systems that report only a single CPU available, platform_smp_prepare_cpus() will never get called. Make sure that tegra_all_cpus_booted is properly set in this case. Change-Id: I6bf30be02c0b692f0578eb9a19062bcb562c1892 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb800c15e27cff51a091e8e704610ed72572b4b6e
2013-09-14ARM: tegra: Fix uniprocessor reset handler initializationScott Williams
- For CONFIG_SMP kernels on systems that only report one CPU available, there is never a call to platform_smp_prepare_cpus() which means the reset handler would not get initialized. Invoke the reset handler initialization from smp_init_cpus() if there is only one CPU. - For non-CONFIG_SMP kernels, the call to initialize the reset handler got accidentally dropped in the port to Linux 2.6.39. Invoke the reset handler initiazation from tegra_init_early() in this case. Change-Id: I782faf84c89d4285aac26bfccb829f27878029de Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9b35221571885a1620e0d7e19880b05a18c97233
2013-09-14ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-24 11:53:48 +0000