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path: root/arch/arm/mach-tegra/platsmp.c
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2012-08-24Revert "arm: tegra: Enable speculative line fill in SCU."Krishna Reddy
This reverts commit 06c880a6086183173c361b4a9d4f8047c6a39769. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I7ff9ffbfe74e2083aa43cab75b694b1c61987bc3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/125097 Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-08-24Revert "arm: tegra: scu: Enable IC and SCU standby"Krishna Reddy
This reverts commit b25193d5c3e2c59169c127d23b59123136cfefa7. This CL is reverted as it causes write perf regression with lmbench(bw_mem) benchmark. Bug 1026077 Change-Id: I9858c88a6e846d2c3629f14c7cc62a7feb4f4528 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/125096 Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-07-23ARM: tegra: power: Enforce CPU rate range in secondary bootAlex Frid
On Tegra3 make sure cpu rate is within G-mode range before LP to G mode switch triggered by secondary cpu boot directly from LP mode. Bug 988544 Change-Id: I0d86fbf0727a6bbf6069159e7c532947a9d0af73 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115930 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Greg Lo <glo@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-05-07arm: tegra: scu: Enable IC and SCU standbyKrishna Reddy
Bug 947861 Change-Id: I1ac97b5de5e7e79a418b3c38c70df4976616cdf3 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/100457 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-29arm: tegra: Enable speculative line fill in SCU.Krishna Reddy
Enable speculative line fill in SCU. Bug 947861 Change-Id: I2db7515c47715160a4e559931e178b41c01a1744 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/91834 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-11-30ARM: tegra: reduce LP0 resume CPU power on timeJin Qian
cherry-picked from adf08ef4030598a6bf9036f45584be8acc008fea Bug 862504 Change-Id: I79460aa4abdccc4f2ca17867197bb12668d59dea Reviewed-on: http://git-master/r/52420 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rffc2d7314a61f04274e0db116c5a1cb7004dc77d
2011-11-30ARM: tegra: Update copyrightsScott Williams
Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/51157 Rebase-Id: R795bf03590a76b6c494afd37603ed951dc2cd082
2011-11-30ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster controlScott Williams
Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48798 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f
2011-11-30ARM: tegra: Avoid timer calibration on slave cpu's.Krishna Reddy
Use the value calibrated by master cpu. Bug 843553 Original-Change-Id: I88939f37050873e0633782f6a927ffaf9b8d776d Reviewed-on: http://git-master/r/47988 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6520764a88346d5ab4a180810636b04ce474f4d7
2011-11-30ARM: tegra: power: Refactored kernel powergate codeKaran Jhavar
This change provides a centralized location for powergating modules. It would take care of switching on/off clocks while un-powergating/ powergating modules respectively. Bug: 814267 Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710 Reviewed-on: http://git-master/r/31776 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
2011-11-30ARM: tegra: Handle uniprocessor all CPUs booted statusScott Williams
For CONFIG_SMP systems that report only a single CPU available, platform_smp_prepare_cpus() will never get called. Make sure that tegra_all_cpus_booted is properly set in this case. Change-Id: I6bf30be02c0b692f0578eb9a19062bcb562c1892 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb800c15e27cff51a091e8e704610ed72572b4b6e
2011-11-30ARM: tegra: Fix uniprocessor reset handler initializationScott Williams
- For CONFIG_SMP kernels on systems that only report one CPU available, there is never a call to platform_smp_prepare_cpus() which means the reset handler would not get initialized. Invoke the reset handler initialization from smp_init_cpus() if there is only one CPU. - For non-CONFIG_SMP kernels, the call to initialize the reset handler got accidentally dropped in the port to Linux 2.6.39. Invoke the reset handler initiazation from tegra_init_early() in this case. Change-Id: I782faf84c89d4285aac26bfccb829f27878029de Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9b35221571885a1620e0d7e19880b05a18c97233
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Trivial changesScott Williams
Change-Id: Id45f6be8336370bf011484bea0a90e7e9f49f026 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R06af455b61cb70a1a7dc18b38ad3f816d4ccba63
2011-11-30ARM: tegra: Consolidate flow control registersScott Williams
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R34a7800e24254d54b499411652d59421be703619
2011-11-30HACK: platsmp.c/pm-t3.c ignore compile errorsDan Willemsen
Rebase-Id: Ra4550b3ee066c825b3484bac1e928fe8c086e0c4
2011-11-30arm: tegra: Clean up SOC conditionalsScott Williams
Change SOC conditionals to make them more forward-looking. Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9 Reviewed-on: http://git-master/r/32706 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998
2011-11-30ARM: tegra: Check if the cpu already booted or notvjagadish
Check the CPU is ever booted before entering into powerup status confirmation loop. BUG 824307 Original-Change-Id: I474d0536b00e84967a240037d2ed984a889dd2e0 Reviewed-on: http://git-master/r/30679 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com> Tested-by: Venkata Jagadish <vjagadish@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R2346bcc108f59eae21cc98a311b95dc702c0a57e
2011-11-30ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
2011-11-30ARM: tegra: Update secondary CPU power up procedureAlex Frid
- Wait for power up status confirmation after secondary CPU was un-gated by flow controller (instead of directly UN-gating CPU again if the 1st status check failed). - Enable CPU clock only after power up is confirmed. - Insert propagation delays before and after removing clamps. Original-Change-Id: I81cd1479bdb49163eeb9a369fc165cede49eb71a Reviewed-on: http://git-master/r/19372 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I061738a5c5f46299cccfcb264d9b5bd838694305 Rebase-Id: R8f3d1364c016aaf4d9856add97612dc7ac77aa6e
2011-11-30arm: tegra: Fix initial boot to LP clusterScott Williams
Forbid cluster switch to G cluster if the G cluster doesn't exist. Bug 791057 Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23 Reviewed-on: http://git-master/r/19302 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9 Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4
2011-11-30arm: tegra: Enable Tegra3 cluster controlScott Williams
Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3 Reviewed-on: http://git-master/r/15269 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae Rebase-Id: R880097280de4f9691f689ab8ab25f08020e98e23
2011-11-30PARTIAL arm: tegra3: Add CPU idle supportScott Williams
Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063 Reviewed-on: http://git-master/r/14167 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6 Rebase-Id: Rb3ac2fff9435330ec65c5541d369b743c9cb898f
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: simplify platsmp.cColin Cross
The synchronization between cpus is handled in the generic ARM code, no need to do it in boot_secondary Change-Id: I2c490823d962c88e177e267c2a46278976925a38 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-11ARM: smp: fix clipping of number of CPUsRussell King
commit a06f916b7a9b57447ceb875eb0a89f1a66b31bca upstream. Rather than clipping the number of CPUs using the compile-time NR_CPUS constant, use the runtime nr_cpu_ids value instead. This allows the nr_cpus command line option to work as expected. Reported-by: Mark Salter <msalter@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-07-26Merge branch 'next/devel' of ↵Linus Torvalds
ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits) ARM: S5P64X0: External Interrupt Support ARM: EXYNOS4: Enable MFC on Samsung NURI ARM: EXYNOS4: Enable MFC on universal_c210 ARM: S5PV210: Enable MFC on Goni ARM: S5P: Add support for MFC device ARM: EXYNOS4: Add support FIMD on SMDKC210 ARM: EXYNOS4: Add platform device and helper functions for FIMD ARM: EXYNOS4: Add resource definition for FIMD ARM: EXYNOS4: Change devname for FIMD clkdev ARM: SAMSUNG: Add IRQ_I2S0 definition ARM: SAMSUNG: Add platform device for idma ARM: EXYNOS4: Add more registers to be saved and restored for PM ARM: EXYNOS4: Add more register addresses of CMU ARM: EXYNOS4: Add platform device for dwmci driver ARM: EXYNOS4: configure rtc-s3c on NURI ARM: EXYNOS4: configure MAX8903 secondary charger on NURI ARM: EXYNOS4: configure ADC on NURI ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs ... Fix up tons of silly conflicts: - arch/arm/mach-davinci/include/mach/psc.h - arch/arm/mach-exynos4/Kconfig - arch/arm/mach-exynos4/mach-smdkc210.c - arch/arm/mach-exynos4/pm.c - arch/arm/mach-imx/mm-imx1.c - arch/arm/mach-imx/mm-imx21.c - arch/arm/mach-imx/mm-imx25.c - arch/arm/mach-imx/mm-imx27.c - arch/arm/mach-imx/mm-imx31.c - arch/arm/mach-imx/mm-imx35.c - arch/arm/mach-mx5/mm.c - arch/arm/mach-s5pv210/mach-goni.c - arch/arm/mm/Kconfig
2011-07-26Merge branch 'next/cross-platform' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: Consolidate the clkdev header files ARM: set vga memory base at run-time ARM: convert PCI defines to variables ARM: pci: make pcibios_assign_all_busses use pci_has_flag ARM: remove unnecessary mach/hardware.h includes pci: move microblaze and powerpc pci flag functions into asm-generic powerpc: rename ppc_pci_*_flags to pci_*_flags Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h
2011-07-12arm,tegra: replace cpu_set() with modern apiKOSAKI Motohiro
cpu_set() is marked as obsolete cpumask function and we plan to remove it in future. This patch replace it with modern cpumask function. Signed-off-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Olof Johansson <olof@lixom.net> Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-tegra@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Colin Cross <ccross@android.com>
2011-07-12ARM: remove unnecessary mach/hardware.h includesRob Herring
Remove some includes of mach/hardware.h which are not needed. hardware.h will be removed completely for tegra and cns3xxx in follow on patch. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-07ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1Stephen Boyd
If an ARM system has multiple cpus in the same socket and the kernel is booted with maxcpus=1, secondary cpus are possible but not present due to how platform_smp_prepare_cpus() is called. Since most typical ARM processors don't actually support physical hotplug, initialize the present map to be equal to the possible map in generic ARM SMP code. Also, always call platform_smp_prepare_cpus() as long as max_cpus is non-zero (0 means no SMP) to allow platform code to do any SMP setup. After applying this patch it's possible to boot an ARM system with maxcpus=1 on the command line and then hotplug in secondary cpus via sysfs. This is more in line with how x86 does things. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-05-23ARM: consolidate SMP cross call implementationRussell King
Rather than having each platform class provide a mach/smp.h header for smp_cross_call(), arrange for them to register the function with the core ARM SMP code instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-06Merge branch 'misc' into develRussell King
Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
2010-12-20ARM: SMP: consolidate trace_hardirqs_off() into common SMP codeRussell King
All platforms call trace_hardirqs_off() in their secondary startup code, so move this into the core SMP code - it doesn't need to be in the per-platform code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: consolidate the common parts of smp_prepare_cpus()Russell King
There is a certain amount of smp_prepare_cpus() which doesn't belong in the platform support code - that is, code which is invariant to the SMP implementation. Move this code into arch/arm/kernel/smp.c, and add a platform_ prefix to the original function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: get rid of references to poke_milo and MiloRussell King
Milo is an old boot loader, which is no longer relevant for these platforms. References to it are misleading. Move the code out of poke_milo(), and remove references to milo in comments. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-20ARM: SMP: Clean up ncores sanity checksRussell King
scu_get_core_count() never returns zero cores, so we don't need to check and correct if ncores is zero. Tegra was missing the check against NR_CPUS, leading to a potential bitfield overflow if this becomes the case. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-14ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_initRussell King
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-08-05[ARM] tegra: SMP supportColin Cross
Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
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