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path: root/arch/arm/mach-tegra/pm-irq.c
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2012-08-07ARM: tegra: lp0 WAKE2 status clearBitan Biswas
Tegra pmc WAKE2 status registers also need to be cleared before re-entering lp0 mode. Change-Id: I1bd5c48baf86ba23d0352594e97c360d363ce991 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/121185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-11ARM: tegra: support multiple wake sources with same irqBitan Biswas
Earlier implementation only allowed single wake source for a particular irq in wake table. Changed implementation to support multiple wake sources ==> single irq mapping. bug 980993 Change-Id: Iacb00487531129ef19c53128824aba802e80350e Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-06-03ARM: tegra: wake up cleanupBitan Biswas
Duplicate functions for wakeup support removed. bug 980993 Change-Id: I1e385a1adec6f2d64ce2c88a59e94d647a16569d Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/105901 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-21arm: tegra: power: clear pmc wake status register on suspendSanjay Singh Rawat
PMC register hold the reason for wakeup from LP0. The keypad driver resume the device from the perspective of the User if the Power Key event is sent in the register. Reset the register before going to suspend so that the status won't get carried to the next wake time as in this case of LP1. Bug 909191 Bug 913110 Change-Id: Ib00b26cd65008327f53b120ca8d0a4dbd3628227 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/68686 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-12-15arm: tegra: irq: PMC WAKE2 level configurationBitan Biswas
Wake level was not getting programmed for wake sources beyond WAKE31. Previous expression was using 32-bit operation. Changing constant 1 to 1ull corrects the calculation. bug 907980 Change-Id: Ie2e5f9a7dd4024db9d96859251169027570540f0 Reviewed-on: http://git-master/r/68907 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2011-12-15arm: tegra: irq: any polarity lp0 wake changeBitan Biswas
False lp0 wakeup due to wake sources configured as any polarity was traced to an earlier change. Reverting the change. bug 906073 bug 909193 Change-Id: I1b2d8ecb265e9a57b5d2514f86853bd59481b58a Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/68700 Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
2011-11-30arm: tegra: power: lp0 wake enable modifiedBitan Biswas
GPIO based lp0 wakeup needed to support search for its irq as well as GPIO bank irq in table. This is implemented in this change. lp0 wakeup irq enable using enable_irq_wake needs to be called in specific drivers. Additionally, in some cases wake irq needs to be updated in tegra wakeup table. bug 890309 bug 902114 Change-Id: I983318172ffb020f565763cfe2bb29018223dcd0 Reviewed-on: http://git-master/r/64395 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rffcadeee341a73f2ea6d62e31d507e9a8dce5a0e
2011-11-30arm: tegra: irq: fix wake level programmingLuke Huang
After toggeling the latchwake_en bit, the status of wake event is latched to pmc_sw_wake_status, not pmc_wake_status. Adding a new function to read out from the proper register. Original-Change-Id: Ib1478504fd16197afe3a2b676833f9ce7f6f7528 Reviewed-on: http://git-master/r/32078 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R371f4cecd474e8e1673e7ae6c465d7907998413f
2011-11-30arm: tegra: Add Tegra3 wakeup sourcesScott Williams
Original-Change-Id: I77cb790db20cc8c8b67069130c0bc8724ba8934e Reviewed-on: http://git-master/r/15027 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I45764ed134dc0be2a21d7641692efb9c847a9b7a Rebase-Id: R0a34fc6fc83145c3720471d359216befb5d0bf5b
2011-11-30ARM: tegra: irq: Add debugfs file to show wake irqsColin Cross
Change-Id: I4a4a05e4b082fff11ed6bd975daebbed31f02a6b Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30ARM: tegra: irq: Add wake irq handlingColin Cross
Add LP0 wake irq handling in pm-irq.c, called from irq.c and gpio.c. Use IRQCHIP_MASK_ON_SUSPEND for LP1 wake irq handling, when the legacy irq controller stays powered. Determine valid suspend modes based on requested wake sources. Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I547bd8290c0921163054d49f43141379e8f9f493