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path: root/arch/arm/mach-tegra/pm-t3.c
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2012-11-21colibri_t30: hack to fix eMMC detectionMarcel Ziswiler
Looks like this DPD stuff whatever it is fails eMMC detection on our current Colibri T30 prototypes. See f4cd0d4448d65a42b65c338f85a3ab8064923c61.
2012-07-20ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-19arm: tegra: PLLX LP/G ports switching ON/OFFPrem Sasidharan
Enable target PLLX port(LP/G) before cluster switch and disable the previous PLLX port(LP/G) after cluster switch is finished. Seeing a power improvement of ~10mW when core operates at max. voltage and max. frequency. Bug 997358 Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com> Change-Id: I9d05245977f9f63a8f4c53b1c6797118d2d8b903 Reviewed-on: http://git-master/r/113399 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16arm: tegra: sd: enable sd dpdWen Yi
This is a WAR solution that allows for the turning on SD DPD feature. The original issue is that enabling SD DPD immediately after device comes out of LP0 causes ULPI disconnect. The root cause of that is not known. The WAR is to delay the enabling of SD DPD for 100ms after device comes out of LP0. Bug 929628 Change-Id: I3c5e35ace422e5441535c2c0fe18545b53bbddc4 Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit bffb7b917d52a3523af80db21322ec7ba5fd33f9) Reviewed-on: http://git-master/r/113392 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16Revert "arm: tegra: power: disable all sd dpd"Bitan Biswas
This reverts commit 8924926cdb77c6ab270867d4caef7a8cdacd11f2. Bug 924452 Bug 929628 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> (cherry picked from commit 142b34993404c853579864f7b7b4f320fb92a715) Change-Id: I9d49703799e32d410beba18938e94e4b641eea6f (cherry picked from commit 8de60b7a832bfbbf09e75def756379dbb2d14c3e) Reviewed-on: http://git-master/r/113387 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-03-14ARM: tegra: power: Use CPU G mode in suspend prepareAlex Frid
Switch to CPU G mode in Tegra3 suspend prepare if CPU suspend rate is high enough. By symmetry, it guarantees that device resume will be happening in G mode as well. Bug 946301 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 082be3604056c39442e1b42f5cfceeb089ffdaae) Change-Id: I42e37ce8847e4916dd0fca9e4bd44096b65f7032 Reviewed-on: http://git-master/r/89352 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-02-23ARM: tegra: power: Notify clock event in CPU mode switchAlex Frid
Add clock event notification to switch timekeeping to broadcast timer during Tegra3 CPU mode switch. Skip notifications if mode switch happens on entry/exit to/from suspend state when timekeeping is already suspended. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 236fd35c40a748d8373d7f34b53c320045fa4d3a) Change-Id: I38386dfe3d4ffb89f35828cd911d254b976f0063 Reviewed-on: http://git-master/r/84713 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-01-30arm: tegra: power: disable all sd dpdBitan Biswas
Disabled dpd support for all SD instances - SDMMC0, SDMMC2 and SDMMC3 bug 924452 Reviewed-on: http://git-master/r/76275 Change-Id: Id8967ccb79fc87fcb249c2a2085cd9d68e1ffcb8 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77304 Reviewed-by: Automatic_Commit_Validation_User
2012-01-04arm: tegra: power: io dpd APIs definedBitan Biswas
Defined IO deep power down(DPD) APIs for tegra drivers - tegra_io_dpd_get - returns dpd handle tegra_io_dpd_enable - enable driver dpd tegra_io_dpd_disable - disables driver dpd bug 919993 Change-Id: I45976b41dca0e3e9266ace86393ef4db8b20c97b Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/72737 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-12-21ARM: tegra: power: Restore IRQ multiple CPU affinityAlex Frid
Restore IRQ affinity to multiple CPUs after LP=>G CPU mode switch. Change-Id: Id7c263f2a11535669d1e9988f4e15b240a7fde38 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/69329 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-12-15ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted. Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-08tegra: treewide: Remove unused gpio-names.h includesDan Willemsen
Most places shouldn't be using these macros, they should get the gpio information from the board files. Either way, all of these instances were unused. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: Ifb76704dccb24e5e6eab4c06c79bc8e97802c6d3 Reviewed-on: http://git-master/r/68481 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-11-30ARM: tegra: power: Restore Tegra3 MC registers after LP0Alex Frid
On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers that are not saved in PMC scratch file for boot-rom restoration. Since SDRAM after LP0 is running at boot rate, MC registers are saved only once during initialization. Bug 874351 (ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d) Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678 Reviewed-on: http://git-master/r/61045 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301
2011-11-30ARM: tegra: power: Force FW bit when SMP is enabled.Alex Frid
Set FW bit in CP15 auxiliary control register after LP=>G CPU mode switch if SMP bit in the same register is set. On Tegra3 in LP mode FW bit is always zero, even though SMP bit is retained. Hence, this change recovers FW bit on return from LP to G-mode. Change-Id: I9f0021ab90866cb8686d73eb6ad5bbedbb2ceb90 Reviewed-on: http://git-master/r/57203 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Tested-by: Antti Miettinen <amiettinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R37dbe2079eafcfb47babaf41b53818a9130d2bbe
2011-11-30ARM: tegra: power: do not check time after kernel time suspendJin Qian
cluster switch for LP0 is called after linux timekeeping suspend, which turns off timer. Bug 862504 Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe Reviewed-on: http://git-master/r/50611 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a
2011-11-30ARM: tegra: power: move cluster switch prolog/epilog from suspendJin Qian
They're called only when doing cluster switch so move them to cluster control function. Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c Reviewed-on: http://git-master/r/49952 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363
2011-11-30ARM: tegra: power: Correct settings for the BURST_POLICY registerYudong Tan
This is needed to allow clusters come up on CLKM Bug 862502 Change-Id: I667cccbf6cbc5af0d47ebc07a5c6c83f14a1cc4c Reviewed-on: http://git-master/r/47584 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2c7ae1605c0d1561c7fa40f45d09ee073d920497
2011-11-30ARM: tegra: power: implement LP1 suspend/resume for Tegra3Yudong Tan
Bug 862502 Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722 Reviewed-on: http://git-master/r/47398 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
2011-11-30ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster controlScott Williams
Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48798 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f
2011-11-30ARM: tegra: power: Don't use suspended kernel timeAlex Frid
Do not use kernel time to time-stamp Tegra3 CPU ULP/G mode switch in late suspend/early resume when timekeeping is suspended. Original-Change-Id: Idb6c8f8c2dd2cfc1e00cec53392de12131d6bbe1 Reviewed-on: http://git-master/r/40958 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R6ce7a5e7e06949f3536524ea675aa9c0fc2ab097
2011-11-30ARM: tegra: power: trace C states and CPU mode switchesPeter De Schrijver
Original-Change-Id: I7915d356f18ac830c93b736463406b907d8c1cef Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/31958 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R341f7619d11f81fd7dfbab2ceb1c6fdaab6ead78
2011-11-30ARM: tegra: power: Overlap Tegra3 cpu off delayAlex Frid
Overlap cpu off delay during G-to-LP mode switch with LP mode residency. Original-Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99 Reviewed-on: http://git-master/r/31641 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R9260cc70b0fd5cf5266c7331a7b37d045f87fbfd
2011-11-30ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13
2011-11-30ARM: tegra: power: cluster control requires CONFIG_PM_SLEEPScott Williams
Change-Id: I6d395efbd8a83d867e6ac645e232ff95538b7f91 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R08fc23af26e1e1b9daf3de235fdd7df8419013de
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: power: Fix CPU complex suspend/resumeScott Williams
- Invoke cpu_pm_enter()/cpu_pm_exit() to save/restore the GIC processor interface registers for the last processor standing from the cluster control interface. - Disable the GIC processor interface on the last processor standing before shutting down the CPU complex so that wakeup interrupts get routed from the legacy interrupt controller to the flow controller. - For Tegra3 enable GIC pass-through mode to prevent WFI failures. Change-Id: Ia866b17bef47fc8e9e75d4e353394b2d1a09259c Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R249fb53a2622218a7128646d68d8a3552268b4f1
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra3: Cluster Switch and LP0 require PM_SLEEPScott Williams
Change-Id: If3d4fa59cf6d7cd8692f6e5b59414a923abcfd0d Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rec3560499e4c64fd76a873689691cbae59f7602b
2011-11-30ARM: tegra: Idle event wakeup timerScott Williams
Change-Id: If072ef10f02d5be7560fdf42584ab11b2a863481 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1ace67e281b1581501aaa936cd9137d326f2c4a
2011-11-30ARM: tegra3: Remove FIXME for LP2 timersDan Willemsen
Now that the LP2 timers exist, remove the FIXME Change-Id: I72e3a5b1aadf79f3adfe40a865ac23c94342cf47 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rceb895f0e2ef1871156a09ff6b582a47907ad3ec
2011-11-30ARM: tegra: update copyrightsScott Williams
Change-Id: If50d29696867787b38febd909910dda75475cc30 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2275ad736d4dbee0a7b716ee6ea19b1863d8d4f8
2011-11-30get tegra3 compilingDan Willemsen
Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac
2011-11-30HACK: platsmp.c/pm-t3.c ignore compile errorsDan Willemsen
Rebase-Id: Ra4550b3ee066c825b3484bac1e928fe8c086e0c4
2011-11-30ARM: tegra: clock: Re-factor Tegra3 cpu clocksAlex Frid
Added second level virtualization (on top of virtual cpu rate control) to support different Tegra3 CPU power modes: low power (LP) mode and geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is defined as a child with two parents: virtual cpu_lp and virtual cpu_g clocks for the respective modes. Mode switch sequence was integrated into cpu_cmplx set parent implementation. (Before this commit mode switch was triggered outside the clock framework, which created cpu clock/mode synchronization problems). Each mode clock is derived from its own super clock mux (cclk_lp and cclk_g) to statically match Tegra3 h/w layout. (Before this commit the code had to dynamically synchronize CPU mode and active mux selection). This change also allowed to support PLLX output divider for low power mode as fixed 1:2 divider with bypass control embedded into cclk_lp parent section. Updated auto and sysfs CPU mode switch calls to use new clock framework, and removed clock manipulation from the low level mode switch implementation. Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
2011-11-30arm: tegra: Enable MC early ACK and scoreboardScott Williams
Bug 791803 Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432 Reviewed-on: http://git-master/r/23584 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2 Rebase-Id: R3308cf0a852ee2bf0e2adb3de17cebc81e48c71c
2011-11-30arm: tegra: Fix initial boot to LP clusterScott Williams
Forbid cluster switch to G cluster if the G cluster doesn't exist. Bug 791057 Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23 Reviewed-on: http://git-master/r/19302 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9 Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4
2011-11-30arm: tegra: Add run-time cluster switch debug controlScott Williams
Allow run-time control of cluster switch debug messages so they can be enabled for debuggability and disabled for performance measurement. Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71 Reviewed-on: http://git-master/r/17927 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379 Rebase-Id: Rb7054dcdd910d9f1b82edb485856e868a47c5034
2011-11-30arm: tegra: Enable Tegra3 cluster controlScott Williams
Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3 Reviewed-on: http://git-master/r/15269 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae Rebase-Id: R880097280de4f9691f689ab8ab25f08020e98e23
2011-11-30ARM: tegra: clock: Update LP-cluster related interfacesAlex Frid
Original-Change-Id: Ifde476a05bd01cdce8c3f4802b268a193a832a1b Reviewed-on: http://git-master/r/14584 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I41204d17c5d8092b1a24b3138efe12cfbd16d7e7 Rebase-Id: R9754ff5e07ecabd945edfccdbc0f9d9586be6e23
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-01 07:19:54 +0000