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2012-09-17arm: tegra: raise cpu floor when display is onWen Yi
When device is idle and display is on, the minimal cpu frequency can drop to 51mhz. Since it takes several tens of millisecond to ramp up cpu freq, the delay impact negatively the performance of low latency CPU bound tasks. Given the power savings of several milliwatts running cpu at 51mhz comparing to 102mhz or 204 mhz at idle, the idle cpu freq is hence raised to 102mhz for smart panel device and 204mhz for dump panel devices. Bug 1036216 Change-Id: Ifb0ed88d4c5fcf5b637d09c587322cec72b8a08d Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit c8465feffcd0cf2401bbd6c6f535955dd68bda55) Reviewed-on: http://git-master/r/132479 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ujjaval Patel <upatel@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-09-06arm: tegra: secureos: disable L2 as part of sleep CPU SMCChris Johnson
This is an alternate way to have the L2 disabled available with later TL secureos versions. In this version, the sleep CPU SMC which is the last one issued before entering LP2 on CPU0, will also disable the L2 without a flush of the secureos workspace. Change-Id: I61c3caade6cb6f922b9d9f9ca0739bc6ae4e78cd Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/128951 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: James Zhao <jamesz@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-08-06arm: tegra: optimize L2 enable/disable paths for secureosHyung Taek Ryoo
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Bug 939415 Signed-off-by: Chris Johnson<cwj@nvidia.com> Change-Id: I756d2ceda83d5d8d6bc5670218e9d874d5e5f62a Reviewed-on: http://git-master/r/119786 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-20ARM: tegra: reset io dpd modeBitan Biswas
Bootloader io dpd settings are cleared during kernel initialization bug 758856 Change-Id: Ic6d5250a5ae127bb45ab37b9200ca06c8d1f11a2 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/115395 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16arm: tegra: cpu: changing cpu min. freq to 51MHzPrem Sasidharan
Changing the CPU min. frequency to 51MHz. This helps in bringing down the core power to 46mW. Bug 1005275 Change-Id: I61daa59866be7baf8ebb741000904422cb095e85 Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com> (cherry picked from commit afbb34d5871b69df328d5aae37f69f25a8946514) Reviewed-on: http://git-master/r/115452 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-06-07ARM: tegra: cpu: enable VDD_CPU rail before LP to G transitionJoseph Lo
When doing LP to G transition, it had a power up latency on VDD_CPU rail. To reduce the latency, CPU_LP can trun on the VDD_CPU rail before the LP to G transition. Bug 930985 Change-Id: I087e185ea5aa90f309b8cafba9bc4bb7d3fc950c Signed-off-by: Joseph Lo <josephl@nvidia.com> Reviewed-on: http://git-master/r/93141 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Antti Miettinen <amiettinen@nvidia.com> Tested-by: Antti Miettinen <amiettinen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-05-21ARM: tegra: decouple mode from flagsBo Yan
When doing LP2 on last standing CPU, we currently pass "mode | flag" to a few functions as argument, with the assumption that "mode" will be confined to lower 22 bits in PMC_CTRL register and "flags" will occupy higher 10 bits. If "flags" grows downward or "mode" grows upward, without this explicit knowledge, LP2 will break on the last standing CPU. Therefore we need to decouple them. Currently only "flags" part is being used when passed to other subroutines, so use "flags" only. Change-Id: I299c998145d81c17760bda8a0b56311fed553958 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/100358 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-14ARM: tegra: pm: suspend trace eventSivaram Nair
A new trace event is added for tracing cpu suspend start and end Change-Id: I2506e3aed0692c44fb4325e9d381cea53228b0c3 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/101748 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-04-24arm: tegra: pm: use writel instead pmc_32kwritelShridhar Rasal
For update of PMC_CTRL register delay is not required. Replacing pmc_32kwritel by writel to improve cluster switch time. bug 954247 Change-Id: Ic39c6fafd606321d549cf26e4cfe662f462b9bdc Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/97229 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-19Revert "ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND"Sang-Hun Lee
This reverts commit e6d0e0ceec7cd1a7b8085eb31d2e70bc4d15684f. Bug 967887 Change-Id: I60927a93ebdf6ba4da14311f8ffcc1edf4f56391 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96788 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: tegra: rethink the cpu suspend-resume code path"Sang-Hun Lee
This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b. Bug 967887 Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96787 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-12tracing: Add tracepoints for cluster switchAntti P Miettinen
Simple trace points for measuring cluster switch latencies. Bug 958262 Change-Id: Ia1e5e13131d5e55aaa0a44e9e8b5196539df54e7 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/93841 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2012-04-05ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/84481 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-05ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPENDVarun Wadekar
Bug 934368 Change-Id: Ic9d75cbb0c324b1858b2e476e33dd4f96349bce3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/86351 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-05arm: tegra: turn off pll-a/p in LP1Mayuresh Kulkarni
- current code does not turn off pll-a/p in LP1 irrespective of voice call status - add a new flag to indicate voice call on-going - use PMC_SCRATCH37 to hold this flag - if it is set, do not turn-off pll-a/p during LP1 - save-restore PMC_SCRATCH37 if it was used to hold the voice call on-going flag - fix few misc formatting issues in tegra3_cpu_clk32k Bug 924817 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/85768 (cherry picked from commit 7853981c987ae329620bb54d869016cb74a6c054) Change-Id: Id5348d2eb44a4bacaf00f6d17edceedaef819e29 Reviewed-on: http://git-master/r/94395 Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-03arm: tegra3: change min_rate for sclkAmit Kamath
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. bug 939415 Original change http://git-master/r/#change,76959 Change-Id: I81cda6a95494764721c1be5b4001c476f3aed6ab Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/93850 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-03arm: tegra: pm: Update CPU complex resumePrashant Gaikwad
Completely removed PLLP restoration from CPU complex resume on Tegra2 platforms (too late: PLLP is restored from AVP warm boot code) Bug 952200 Bug 931285 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/92523 (cherry picked from commit 066dc172010f1a5ea5a375e1cbdcf162ab206d63) Change-Id: I1a31793db8ee1fda5a947d69890e3118f0d3cdab Reviewed-on: http://git-master/r/93562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-03-15ARM: tegra: power: Set awake system CPU rate floorWen Yi
Set CPU rate floor to 100MHz when the system is awake (after boot, or on late resume). Remove the floor when the system enters early suspend. Bug 922351 Change-Id: Ibaca50791a5b04b4b4165ceac5018d4cfd7c1bcf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/89587 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-14ARM: tegra: power: Boost CPU rate before device resumeAlex Frid
Boost CPU frequency in tegra platform resume finish phase, just before driver resume. Boost level is specified by platform suspend data (ignored if 0). Bug 946301 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59) Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e Reviewed-on: http://git-master/r/89353 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-03-13ARM: tegra: pm: only identity map lowmem areaRay Poudrier
Bug 941380 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/87095 (cherry picked from commit 72b72afb18f852ee0b352b0644bf30b4afeaa055) Change-Id: I7e10b6180044a6fb58b2fee835991812c193d9b1 Reviewed-on: http://git-master/r/89564 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2012-03-07ARM: tegra: Clean kernel and I/O mappings upon LP2Antti P Miettinen
There is no need to flush the complete L2 upon LP2 entry but it is necessary to clean the page table entries needed by LP2 code sequence that has L2 off and MMU on. Bug 931316 Change-Id: Ice353f16d35ee24d4387e7b9b135f205c4d0ba32 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/86293 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-02arm: tegra: power: disable SUSPEND_LP2 mode selectionAshwini Ghuge
Disable selection of LP2 suspend mode from sysfs and if LP2 mode set from board file change mode to LP0 Bug 928456 Change-Id: I1603153e23688ff1048289c4e04f7c7337f480af Reviewed-on: http://git-master/r/86580 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-01ARM: tegra: Add support for passing arguments to bootloader.Gaurav Sarode
PMC SCRATCH register 0 holds value across warmboot. Storing values in bit31:30 for recovery and fastboot. This requires change in bootloader as well to parse these arguments. Bug 863014 Change-Id: I1d4b752dbc6dd7b065e9d0cc87df189e7caeb201 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-on: http://git-master/r/86140 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-01ARM: tegra: power: Fix Tegra2 power timer rateAlex Frid
Commit cb0428145196ed7a75861c78d28f46b6bc8d2320 implemented LP0 state entry with fast CPU and system bus clocks only for Tegra3, but changed power timers rate calculation in the common Tegra2 and Tegra3 path. Fixing it now. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 9e66d6adf6ab1fe06eee63baf0f1f684715d1ae2) Change-Id: Iac276f048fed4edbee318cadddb862e45ba851c6 Reviewed-on: http://git-master/r/86550 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-23ARM: tegra: power: Don't lower clocks on LP0 entryAlex Frid
Do not change (lower) CPU and system clocks, and do not disable PLLs on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1) Change-Id: I2f175882d4d3dcfe5aee9c460f873a5e907e4ece Reviewed-on: http://git-master/r/84714 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-02-23ARM: tegra: clock: Update secondary pll dividers resumeAlex Frid
During resume from LP0 on Tegra3 always enable pll secondary dividers before clocks restoration (to make sure clock sources are enabled). Restore actual secondary dividers settings after clocks are restored. Remove pllp secondary dividers restoration from cpu complex restore, and add them to common clock restoration procedure. These dividers are not affected by CPU complex suspend, only by LP0 core suspend. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 1f631436717c0602ef30770f7976615150114afe) Change-Id: I45777ca0535f51a39c35e9d360ac6e97a13ea92c Reviewed-on: http://git-master/r/84712 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-02-17Revert "arm: tegra3: change min_rate for sclk"Chandrakanth Gorantla
This reverts commit a61ef84d7746134aae316fa76867d69fc0753880. Bug 939415 Change-Id: I7d7c2a69ac7261a221cf69b8f8981d42f575f789 Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-on: http://git-master/r/84025 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-13ARM: tegra: Clean up CACHE_L2X0 conditionals and includesScott Williams
Change-Id: I9862e73f264c757f97aaad03f3373fb1d3e95462 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/79138 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-03ARM: tegra: power: Update CPU complex resumeAlex Frid
- Completely removed PLLP restoration from CPU complex resume on Tegra3 platforms (too late: if necessary PLLP is restored by LPx exit code on Tegra3, and attempt to restore it again does not do any good). - Restored PLLX only if it is not already used as CPU source (it is dangerous to restore PLL in use). - Restore burst policy on exit from LPx states, but preserve it after cluster switch, as it maybe different for LP and G clusters. Reviewed-on: http://git-master/r/72535 Change-Id: Ia5ff24d22a2135494bc3442f92bebcc1953c7f08 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78702 Reviewed-by: Automatic_Commit_Validation_User
2012-01-31ARM: tegra: power: Set awake system CPU rate floorAlex Frid
Set CPU rate floor to 100MHz when the system is awake (after boot, or on late resume). Remove the floor when the system enters early suspend. Bug 922351 Reviewed-on: http://git-master/r/77444 Change-Id: I68f54a3d981c1cbeac16d58d3beb6e3aa6bf190c Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78031 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-31arm: tegra3: change min_rate for sclkWen Yi
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. BUG 922351 Reviewed-on: http://git-master/r/76959 Change-Id: I6a2871d1cc02a19829cf397e9583122e02255f81 Signed-off-by: Wen Yi <wyi@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78010 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-30arm: tegra: power: disable SUSPEND_NONE mode selectionBitan Biswas
sysfs interface to select suspend mode as TEGRA_SUSPEND_NONE is disabled. Additionally, if tegra_suspend_dram is called with suspend mode as TEGRA_SUSPEND_NONE we return error bug 927937 Reviewed-on: http://git-master/r/77268 Change-Id: Ifdd57cdf27e739a9c093cad4eddefb73a6a2355d Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77757 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30arm: tegra: Fix setting CPU_RESETTABLE_SOON flagJoshua Cha
tegra2_cpu_set_resettable_soon() should be called in CPU1 only. Reviewed-on: http://git-master/r/75517 Change-Id: I0825a2d2ed2935d2b1dac1ff7d134e1f4f37f552 Signed-off-by: Joshua Cha <joshuac@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77751 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30ARM: tegra: power: Fix warnings when PM_SLEEP is not selectedScott Williams
Reviewed-on: http://git-master/r/76686 Change-Id: I88939c92aa1c28f5177010ba2afd524c3a4b713d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77738 Reviewed-by: Automatic_Commit_Validation_User
2012-01-04arm: tegra: delete the debugfs sys entry for suspendVandana Salve
Deleted the tegra debugfs /sys entry. Instead have a unified /sys/power/suspend/mode sysfs entry to set the suspend state. Bug 911096 Change-Id: I280eb0ed0f5c8b46c2147d84c27b1cf728078709 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/72419 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-12-15ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted. Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/67340 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-08arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-12-08arm: tegra: Set G-CPU L2 cache latency to 0x442/552.Krishna Reddy
also restore the L2 cache latency values after exit from LP2. Bug 909628 Change-Id: Ia113d3511255f77ba5f5bfbfafebe43ba247818f Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/67767 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30ARM: tegra: power: omit L2 flush for LP2Antti P Miettinen
The L2 cache RAM is preserved over LP2 so omit the L2 cache flush in tegra_idle_lp2_last(). Bug 880338 Change-Id: I6aa30c712b6e467bd48e9c1959da2a69453a8f43 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/59892 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6eee47d009d45d0e20254a97df919bf2fc34e6cd
2011-11-30ARM: tegra: power: add combined power req processingJoshua Cha
For platforms where the core & CPU power requests are combined as a single request to the PMU, we need separate processing to enable its suspend/resume operation. Bug 862504 Change-Id: If66282a7b069d35568147e2d64f14371e1692bfd Reviewed-on: http://git-master/r/64011 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R21b966a438be03b11b80ce7deb70e3036b80dab2
2011-11-30ARM: tegra: uart: Restore FCR in uart resumePradeep Goudagunta
Restore FCR while resuming debug uart, to enable RX and TX FIFOs with trigger levels configured during initialisation of debug uart port. Bug 867063 Change-Id: I9665ff29a53c3e2e6c78a3037e20e7362a642f77 Reviewed-on: http://git-master/r/62411 Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: Ra3b9858456b952ab539a36019a55863077094054
2011-11-30ARM: tegra: timer: Update twd suspend/resumeAlex Frid
- Preserve twd periodic load register across suspend and LP2 on main CPU. Keep timer disabled on resume, since it will be re-configured later when timekeeping switches from global system timer. - Generate "load equal zero" warning in twd suspend/resume code only when timer is in periodic mode. Change-Id: If7df8be08c0ef4e355f315e3f0b7e3cf1b358f0f Reviewed-on: http://git-master/r/55068 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R75f3950a915e0953a098620dea9ea32a7d5e9482
2011-11-30ARM: tegra: power: fix build error on tegra_pm_enter routinesJin Qian
Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c Reviewed-on: http://git-master/r/51852 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861
2011-11-30ARM: tegra: power: save cluster switch status before entering LP0Jin Qian
warm boot reads SCRATCH4 to choose wake-up from LP or G Bug 862504 Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a Reviewed-on: http://git-master/r/50610 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94
2011-11-30ARM: tegra: power: move cluster switch to syscore for LP0Jin Qian
move printk as well since they rely on uart resume in syscore Bug 862504 Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e Reviewed-on: http://git-master/r/50240 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b
2011-11-30ARM: tegra: power: move cluster switch prolog/epilog from suspendJin Qian
They're called only when doing cluster switch so move them to cluster control function. Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c Reviewed-on: http://git-master/r/49952 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363
2011-11-30ARM: tegra: power: restore reset handler after lp0Jin Qian
Bug 862504 Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7 Reviewed-on: http://git-master/r/50241 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400
2011-11-30ARM: tegra: power: Call cluster_switch_prolog/epilog for LP1Yudong Tan
cluster_switch_prolog is needed to set up car/flow controller registers for LP1 entry. epilog is needed to clean up some flags in flow controller after LP1 exit. Bug 862502 Change-Id: Ib9eeac6fc541cfa644d782071dbd4187255404d8 Reviewed-on: http://git-master/r/47585 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2c72673ba1b7f04ffa1b760ff54aaf73cf23f09e
2011-11-30ARM: tegra: power: implement LP1 suspend/resume for Tegra3Yudong Tan
Bug 862502 Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722 Reviewed-on: http://git-master/r/47398 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-21 14:56:34 +0000