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2014-06-12arm: tegra: pm: add delay between writes to IO_DPD_REQJay Cheng
SW should explicity add delay between writes to IO_DPD_REQ and IO_DPD2_REQ registers. This is because we use the same state machine for both the registers. The time between writes should be apb clk * (SEL_DPD_TIM + 5). The worse case of apb clk is 32Khz, SEL_DPD_TIM is configured as 0x10. delay = (1/32000) * (16 + 5) which approximately 700us. Bug 200002717 Change-Id: Icf4efdbc38ccdaca30a9d86da488ac796b657b36 Signed-off-by: Jay Cheng <jacheng@nvidia.com> Reviewed-on: http://git-master/r/411065 (cherry picked from commit ebba7445ff9a32af6bb1759ac70311f66e2986cb) Reviewed-on: http://git-master/r/412826 Reviewed-on: http://git-master/r/418379 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-06-03arm: tegra: pm: suppress kmemleak false positiveAllen Yu
The memory block for relocating lp0 vector is referenced by a physical address (i.e. tegra_lp0_vec_start) which kmemleak can't detect. Mark it as not a leak to avoid false positive. Bug 200007297 Change-Id: Ie137f08d77911677d9e76fdb7d0112a1610dd72d Signed-off-by: Allen Yu <alleny@nvidia.com> Reviewed-on: http://git-master/r/415032 (cherry picked from commit 60520279ce2d6081a87a1bc1127046223b3839f6) Reviewed-on: http://git-master/r/416824 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2014-05-27misc: Align spacing with dev-kernelDan Willemsen
When these changes were integrated, spacing was fixed. Propagate those fixes back to rel-21. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I49102bbf7571a6158fe7c0dd2c4d413ef5462334 Reviewed-on: http://git-master/r/409758 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
2014-05-16arm: tegra: pm: move err print to debug printBibek Basu
Unwanted print, that too with err level is moved to debug level Bug 1501662 Change-Id: I0fbfa966ab69ec40dd4a218e4e03226ab197a8da Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/408038 (cherry picked from commit c01a80c066f97e34f1850c705b9022a9165638bd) Reviewed-on: http://git-master/r/409205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-04-28Revert "Revert "ARM: tegra: pm: turn off VDEC partition in LP1""Allen Yu
This reverts commit 193e70e3a74bb167e4a443329dc0bd3cf0fcd7a0. VDE partition has to be left on before entering LP0, otherwise secure content playback may be corrupted after resuming from LP0. So we unpowergate vde in the dependent change. This change turn off vde partition specifically for LP1 case to save power. Bug 1502013 Bug 1507043 Change-Id: Ibf1dcb40a33cb52f9366e250452a54ae43fcb67a Signed-off-by: Allen Yu <alleny@nvidia.com> Reviewed-on: http://git-master/r/401253 (cherry picked from commit f8b07f13193c1bdd2c76c6dc2520ee66c12b8790) Reviewed-on: http://git-master/r/401983 Tested-by: Praveen Kumar Reddy M.V. <pkreddy@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-04-23platform: tegra: move LP0 entry function to driverPrashant Gaikwad
Change-Id: Ife6926d0c00d7e046b2579795f50ef96d633fc8f Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395845 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-04-13platform: tegra: move pm_domain to driversPrashant Gaikwad
Change-Id: I30baee4084399b8078232f31296c4d891a903d47 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395123 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-03-25ARM: tegra: pmc: deleting pmc.h from mach-tegra/Sumit Singh
Moving the content of pmc.h to linux/tegra-pmc.h and deleting it. Bug 1440573 Change-Id: I54014c58765b99dd99e6aaae22bad8cb9010e79c Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/377592 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-03-14ARM: tegra: remove CONFIG_USE_SECURE_KERNEL usageVarun Wadekar
Remove the config variable usage from the kernel and make the secure firmware check dynamic. This make LP1 resume tricky since we need to execute out of TZRAM till SDRAM is out of self-refresh. To fix this, store secure firmware presence bit in TZRAM during boot. Bug 1475528 Change-Id: Ic18766bbee14626e8cf092363d57f4d98b44b6df Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/377616
2014-03-14arm: tegra: use PSCI interfacesVarun Wadekar
ARM defines PSCI interfaces to be used for power states. We have been using the actual semantics for quite some time now and so can remove our implementation of the SMC issuing code and use the generic interfaces present in <arm/arm64>/kernel/psci.c. Bug 1475528 Change-Id: Ieba8a0a54f5ee731626e7d92a767ef044e88f12d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/378354
2014-03-13Revert "ARM: tegra: pm: turn off VDEC partition in LP1"Allen Yu
This reverts commit ff4983e5bf793f1abdd8e325abdbd254256f80e3. There is no need to powergate VDE specifically in LP1 now since the dependent change has removed the unpowergating statement in avp suspend callback. VDE powergating in LP1 will be taken care of in the common suspend callback. Bug 1455975 Change-Id: Ibed11846064c1a2cdab6fb311767bcc0f90d4976 Signed-off-by: Allen Yu <alleny@nvidia.com> Reviewed-on: http://git-master/r/380414 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-02-16arm: tegra: call PM notifier before LP0 entryPrashant Gaikwad
Some devices does not save complete state in runtime suspend and are supposed to be suspended when IRQs are disabled. Such kind of devices can register to this notifier which are expected to save their state before going in LP0 from idle state. Bug 1254633 Change-Id: Ic134c6036492a0f032b3d2e63d1dc531a40bc3b4 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/367580 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-02-09Revert "ARM: tegra: trustzone: Single kernel to work in both secure and ↵Varun Wadekar
non-secure mode." This reverts commit 7f93a0dddf39f372c064f772f9af6903e91aaacf as the t132ref builds break with the following errors - <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:45: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:57: undefined reference to `is_secure_mode' <android>/kernel/drivers/platform/tegra/../../../arch/arm/mach-tegra/reset.c:58: undefined reference to `tegra_generic_smc' Change-Id: I4e44c2ffba4e1c013213e543b67f2d49a928b764 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/365347
2014-02-09ARM: tegra: trustzone: Single kernel to work in both secure and non-secure mode.Nitin Sehgal
- Remove CONFIG_TEGRA_USE_SECURE_KERNEL config option - Use DBGDSCR.NS bit to dynamically get secure/non-secure mode - Replace ifdefs with dynamic code. - Keep CONFIG_TRUSTED_LITTLE_KERNEL to enable secure os bug 1411345 Change-Id: I75ddfed7a35fcb30e2772bb43057ae022bcf09b3 Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com> Reviewed-on: http://git-master/r/353155 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2014-01-21ARM: tegra: fix identity_map_add call for ARM64Peng Du
Change-Id: Ib6beca28f413597f84b3b1a8bebd4f9de4aaf94c Signed-off-by: Peng Du <pdu@nvidia.com>
2014-01-21FIXUP: ARM: tegra: fix arch header includes for ARM64Alex Van Brunt
Change-Id: I0326b9e22688f236ee961b6c8e6670e322be4d7c
2014-01-21ARM: tegra: fix platform drivers for ARM64Peng Du
Change-Id: I03dae90251ce6c2cf0c0a237ebe0cf53bda9d57d Reviewed-on: http://git-master/r/200297 Reviewed-on: http://git-master/r/225393 Signed-off-by: Peng Du <pdu@nvidia.com>
2014-01-13arm: tegra: fix warning to enable -WerrorAjay Nandakumar
Fix various warnings to enable -Werror option. Bug 1211919 Change-Id: I913728fd3f2cbac0243b4e116c53cb035ed17f35 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/354292 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2014-01-10ARM: tegra: dvfs: Update DFLL bypass detectionAlex Frid
With multiple Tegra12 platforms support in one kernel image, using DFLL bypass config option is not sufficient to properly differentiate platforms with DFLL bypass. Added platform data check to DFLL bypass detection interface. Change-Id: I7a20561ef7aa155fb5bcfa310bb8ee7d79711bfb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/353934 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2014-01-03ARM: tegra: pinmux: correct pinmux resume sequenceMohan T
Do not operate on DPD pads and do not TRISTATE pins before restoring for T124 Bug 1416263 Bug 1429819 Change-Id: I7261c7e5d4341f6d74dadf1ab6af985e7965b860 Signed-off-by: Mohan T <mohant@nvidia.com> Reviewed-on: http://git-master/r/351369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com>
2013-12-31arm: tegra: pm: switch print statementsPrashant Gaikwad
Move the print for suspend state after changing CPU mode so that it appears after cluster switch print in case of LP0. It was confusing for some users if CPU was switching cluster after entering LP0. Change-Id: I2b02fa8b70bd110b4386c235c5521730b6cc7536 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/350961 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-12-03arm: tegra: use ARM's DEN0028 v0.9 and PSCI specs to define SMCsVarun Wadekar
Use SIP Service calls (0x82000000x) and Standard Service calls (0x8400000x) from the DEN0028 spec. PSCI says that we need to use 0x8400000x in r0 for any power management features i.e. cpu idle/hotplug/on/off followed by the actual cpu state (LP2/LP1/LP0) in r1. This translates to Std service calls space mentioned in the DEN0028 spec. The SIP service calls can be used by silicon partners for their CPU specific settings. We use this SMC space for L2 settings and to set the CPU reset vector. SMCs that are interrupted return a special status code to the NS world. Look for that status and send a restart SMC (value = 60 << 24) when received. Also removed save/restore of r4-r12 as we rely on the secure OS to do this for us. Change-Id: I6fae83cc96d29c23305177df770fa07f7970c383 Signed-off-by: Scott Long <scottl@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/329998
2013-11-05ARM: tegra: RODATA: Fix for normal OSAntti P Miettinen
The tegra_generic_smc is not present in normal OS. Change-Id: I5d265841cfb6fc1ebe8fe51b9341fab408ef7ddc Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/326083 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
2013-11-05fuse: cleanup unwanted fuse related dataShardar Shariff Md
cleanup of unwanted fuse related data as a part of migration of fuse driver Bug 1380004 Change-Id: I78ff9f6b1d3a27ae0ba0369ad9692c40e9e24bfd Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/310037 Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-11-04arm: tegra: add function to enter LP0 from cpuidlePrashant Gaikwad
Bug 1254633 Change-Id: I8c69d238877615a594bed6542462873f897e0ad4 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/309496 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-31arm: tegra: add tegra pm notifierPrashant Gaikwad
Add PM notifier to suspend/resume device for LP0 in idle. Bug 1254633 Change-Id: I4b6e7e1a00202ab6a4fe6eb12110b82b92589766 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/309617 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-28ARM: tegra: Move mach-tegra/{gic.h, pm-irq.h}Ajay Nandakumar
Moving mach-tegra/gic.h and mach-tegra/pm-irq.h to include/linux/irqchip/tegra-irq.h so that it helps faclitate the movement of irq drivers from mach-tegra/ to drivers/. Bug 1379891 Change-Id: Id062ebc16441ac295df78731c1e44b32e75d3286 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/302884 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-21ARM: Tegra: Cautious debugging in early resumeAntti P Miettinen
Doing prints early in resume can be costly. Let's use pr_debug instead of pr_info. Bug 1381343 Change-Id: I5fdc61e7cc95d0864e2e81e36c8b6b2a425fb356 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/299970 (cherry picked from commit cf28de40659781154ebdfed922900b160912a3ca) Reviewed-on: http://git-master/r/301523 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-18ARM: Tegra: Utilize burst policy for LP1 wakeupAntti P Miettinen
Running SCLK from CLKS makes LP1 wakeup latencies horrible. However, we can utilize IRQ bursting to switch automatically to CLKM upon LP1 wakeup IRQ. This maintains low power for LP1 but improves wakeup latencies significantly. Bug 1381343 Change-Id: I9a3fcd81999d1b593bf242bfa7ef8505f9848d43 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/298749 Reviewed-by: Bo Yan <byan@nvidia.com>
2013-10-17ARM: tegra: power: Don't change mode of uninitialized DFLLAlex Frid
If DFLL has not initialized, yet, or initialization failed: - do not change DFLL mode from sysfs callback - do not resume DFLL bypass mode after CPU rail gating/cluster switch Change-Id: Ife68679b942e9af30cdc7dddbec1abf15f42dd66 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/299264 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-10-17ARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}Ajay Nandakumar
Moving mach-tegra/clock.h and mach-tegra/timer.h to include/linux/tegra-cpuidle.h and include/linux/tegra-timer.h so that it helps faclitate the movement of drivers from mach-tegra/ to drivers/. Bug 1379817 Change-Id: Ia0a33c3f726d2f672409c270ac8ca1629f05eff8 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: http://git-master/r/299019 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-16arm: tegra: register save and restore opsPrashant Gaikwad
Register syscore ops for modules whose context has to saved/restore during entry/exit to LP0 state from CPU Idle. Bug 1254633 Change-Id: Idf4a67535754db3ccc2fc528469fb17ec198cee0 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/299447 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-16arm: tegra: update power state residencyPrashant Gaikwad
Update minimum residency expected for different power states as derived from analysis done in bug 1347388 Bug 1347388 Change-Id: Ifd3d1e68d58a3c0bf5015b33be5ed8c926dd1e91 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/299462 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-10-01ARM: tegra Fix warnings in compiling pm.cPhilip Rakity
remove unnecesssary typecast in pmc_read/write remove typecast printk for phys_addr_t Change-Id: I161ddb3f34ae5bb54845fb9bac507a125f5ebddb Signed-off-by: Philip Rakity <prakity@nvidia.com> Reviewed-on: http://git-master/r/270754 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> (cherry picked from commit 246be84a48c706e19e8bcb1c5c4127f89d8761e3) Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
2013-09-27ARM: tegra: RODATA: SMC stack RWHiroshi Doyu
With DEBUG_RODATA, .text section is set as read-only. This prevents SMC call from using stack with CONFIG_TEGRA_USE_SECURE_KERNEL. This patch set SMC stack {read,write}'able exceptionaly for DEBUG_RODATA. Bug 1365298 Change-Id: I4a18886e5eb0c4f1ca3696d4621bd882dc528e48 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/276539 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-09-26ARM: tegra: Fix incorrect pointer cast warningsAlex Frid
Change-Id: Ib239cc7ffe37ca5873c2116561bb8d85e70a4fb0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/274749 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-16ARM: tegra: dvfs: Account for GPU rail suspend timeAlex Frid
Change-Id: Icefd90ebe4ae5bcad89e3a61b1c2fc69cded90b5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/272874 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-16ARM: tegra: pmc: T12x wake status clear fixBitan Biswas
Problem: T12x PMC Wake status gets cleared during LP0 resume Cause: During LP0 resume, T12x APBDEV_PMC_DPD_ENABLE_0 register's TSC_MULT_EN bit needs to be programmed after DPD_ENABLE is cleared. Fix: Cleared the DPD_ENABLE bit along with TSC_MULT_EN bit clear during LP0 resume for T12x bug 1367291 Change-Id: Ifcc25709ffb012b4e6d4d0bb325f12d1ede94413 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/273646 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-09-16ARM: tegra: power: Fix suspend initializationAlex Frid
Added initialization for crail suspend platform data entries missed by commit 14ddff697632b88f1f89aa2c62f5a053e37c7e27. Moved CL-DVFS initialization to regulator init call (from fixed regulator init) to setup dfll bypass call-backs before suspend initialization. Bug 1351735 Change-Id: Ia4bbf260873630db40e7fdf0966cd319fe265a4f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/270294 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>Dan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
2013-09-14ARM: tegra: Move mach/powergate.h to linux/tegra-powergate.hDan Willemsen
This moved upstream, do the equivalent change here. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I2de76e5c6487ed4513b6d070e0c515a27a881fff
2013-09-14ARM: tegra: Use <linux/clk/tegra.h> instead of <mach/clk.h>Dan Willemsen
So that the upstream common clk infrastructure can live side by side. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I0fe0ef8cd207d27b707821eed838c75b8ec04025
2013-09-14ARM: Tegra: Move cluster switch tracepointsAntti P Miettinen
Move tracepoints for measuring cluster switch latency to account for the whole interrupts-disabled time. Change-Id: Ib49cc54078d2e284c34b55dd6e2dc57431706b78 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/264800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
2013-09-14ARM: tegra: PMC DT supportBitan Biswas
PMC DT support changes are as follows: - Downstream code needs local changes in addition to upstream PMC DT support change to compile fine. Common clock framework (CCF) is not enabled downstream today as a result we cannot switch to upstream version of the function set_power_timers today. - All PMC platform data from board files is not available in DT bindings upstream. Using the board passed values in such cases to ensure that functionality is intact. - Further, if DT attribute values do not match board platform data settings the board setting is used for the time being. bug 1173104 Change-Id: Ife63ab84178c5aa4371bfee188ce919a99f651fc Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/263727
2013-09-14ARM: tegra: moving the CPU power timer function to PMC driverJoseph Lo
The CPU power timer set up function was related to PMC register. Now moving it to PMC driver. And it also help to clean up the PM related code later. The timer was calculated based on the input clock of PMC. In this patch, we also get the clock from DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> (cherry picked from commit 0337c3e0c3cbbb3a4f411c292f52fcc314abae67) bug 1173104 Change-Id: I03a80b2c0cfcb5223b1b113f395ef3899eafd06e Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/263722
2013-09-14ARM: tegra: power: Support CPU rail early startupAlex Frid
Added an option for cluster switch procedure to turn CPU rail ON via direct access to PMC registers before disabling interrupts, and then continue scheduler execution while the rail is ramping up. RAM repair is executed in s/w as well after rail ramp is done. Only non-CPU partition is power-gated/un-gated by flow controller in the atomic section. However, rail ramp in this case is serialized with CPU save context. Hence the trade-off: early startup option reduces interrupt disabled time during cluster switch, but increases overall cluster switch time. Bug 1351735 Change-Id: I5ff9afb2aa6b27b9aa4b2318ee2740dee4908e2f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262864 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: power: Add cluster switch time statsAlex Frid
Expanded cluster switch instrumentation with simple timing statistic: running window average, exponential average, maximum switch time - aggregated separately for LP/G and G/LP cluster switch. Added the respective debugfs node. Moved cluster switch start/end timing samples to exactly match interrupt-disabled section of the switch. Replaced cluster instrumentation error message with debug print. The INSTRUMENT_CLUSTER_SWITCH compile option is still disabled, so by default all changes in this commit are not compiled in. Change-Id: If7b9c7b1469f6839e20b7c8db3aa9cf2c0592f2d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/262859 Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: power: Use rate as pmc register update selectorAlex Frid
Used minimum emc rate required for modem operations in LP1BB/LP0BB to select emc configuration data block loaded into pmc scratch registers before entry to LP0 (this commit provides only template for selection: block 1 is always selected, for now). Bug 1319638 Change-Id: I0b0322d0d0749356052418d9bf9e3b9f9edf416e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/245672 (cherry picked from commit 21843bddaebf3fc2122ae0943b6a56c4fb02aebc) Reviewed-on: http://git-master/r/262033 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra14: clock: Update EMC suspend configurationAlex Frid
- Set EMC suspend rate to minimum requested by base-band controller - Specify LP1BB voltage level based on EMC suspend rate (will actually be set by LP1BB entry code) Bug 1300939 Change-Id: Ida480539b5a71e13bfd8d00bb19724f4f85927e6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/240305 (cherry picked from commit 4777a040200d582b318ccb247299ddcd4675ac5d) Reviewed-on: http://git-master/r/262031 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2013-09-14ARM: tegra: dvfs: Suspend DFLL bypass on LP CPUAlex Frid
Suspended DFLL bypass when LP CPU cluster is powered down always, even if DFLL will be used as CPU clock source after the switch to G CPU cluster. This change guarantees safe LP to G cluster switch in case when DFLL bypass was engaged via sysfs nodes while running on LP CPU. Bug 1310396 Change-Id: I768f04be2cd9dd5d01be2f9f287c57ff71d5542d Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/260865 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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