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2011-11-30arm: tegra: Console suspend for all boardsLaxman Dewangan
Added the board level suspend/resume and call the console suspend from board level suspend/resume. bug 820536 Original-Change-Id: I246265241246dc0682870571c927bd23023e5aca Reviewed-on: http://git-master/r/41448 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Re1f3dd4f75ee05456899d9a67f74ae84f9572654
2011-11-30arm: tegra: suspend: Add board specific suspend/resume callsLaxman Dewangan
Adding board specific suspend and resume call apis through platform data. Added call of these function at appropriate stage of suspend/resume. Added mechanism to select the uart debug channel base address through variable so that board file can directly change this. bug 820536 bug 832273 Original-Change-Id: Ia9ff3b8a8d2faa1071a8ff634960e6a6c8a43d40 Reviewed-on: http://git-master/r/34494 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6d7bfb3f8f9152779f5138cbcd1b7a9e9a9545df
2011-11-30tegra: power: correct LP0 sequenceJay Cheng
Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7 Reviewed-on: http://git-master/r/47365 Tested-by: Cho-Che Cheng <jacheng@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e
2011-11-30ARM: tegra: power: setup TTB0 for cacheable memoryJin Qian
Bug 862494 Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3 Reviewed-on: http://git-master/r/47246 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58
2011-11-30ARM: tegra: power: Overlap Tegra3 cpu off delayAlex Frid
Overlap cpu off delay during G-to-LP mode switch with LP mode residency. Original-Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99 Reviewed-on: http://git-master/r/31641 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R9260cc70b0fd5cf5266c7331a7b37d045f87fbfd
2011-11-30ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13
2011-11-30ARM: tegra: sysfs write permission for user onlySachin Nikam
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. - tegra_mc_stats: enable and quantum - susend: mode - clock: rate, parent, state File System Permission CTS expects this to pass. Bug 840409 Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/36867 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb
2011-11-30arm: tegra: power: fix lp0 resume failureLuke Huang
Do not check PLLX lock bit on PLLX sanity check, since it might not be in the lock state yet. Original-Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3 Reviewed-on: http://git-master/r/35261 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R1ea05b0640b93de011109de3402d8810a64defcc
2011-11-30ARM: tegra: power: use buffered memory for suspend contextJin Qian
use buffered memory to bypass L2 add memory barrier after cpu suspend Bug 862494 Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe Reviewed-on: http://git-master/r/47172 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7
2011-11-30ARM: tegra2: power: Fix reset race condition between the CPUsScott Williams
During LP2 for CPU idle on Tegra2, there could be a race condition between the CPUs. CPU1 cannot autonomously shut itself down (put itself into reset). CPU1 must be reset by CPU0 but only when it has no outstanding memory or I/O transactions going on (i.e., it is in the WFI state). CPU1 indicates its readiness to be reset by setting status in a PMC scratch register. If CPU1 wakes up and CPU0 sees CPU1's ready to be reset status before CPU1 can clear it CPU1 could be reset at inappropriate times resulting in loss of cache coherency and ultimately a kernel panic. Eliminate the race condition by ensuring that: - CPU1's reset ready status is cleared as early as possible before CPU1 rejoins the coherent world. - Use writel when updating the IRAM LP2 status flags to ensure the IRAM and coherent memory views of the flags are consistent. - If there is not enough time remaining for CPU1 to be in LP2 for the minimum residency time, clear CPU1's reset status flag before entering WFI so that CPU0 will not wait for CPU1 to be ready to reset (since it won't be if there is insufficient time). Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848
2011-11-30ARM: tegra: power: Map the CPU context page to tegra_pgdScott Williams
Add a mapping of the page used to save the CPU context to the private pgd used during MMU shutdown. Change-Id: I10ef282ff15ff5ee8469fcaa3637bcb0fb39ba4d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R837a2eb005ad93ef206153b120e972ee65383b65
2011-11-30ARM: tegra: power: Consolidate PM_SLEEP conditionalsScott Williams
Change-Id: If8f8868d929ec5bebe7c0083e03af504c7a6af11 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rf382a5bf2c7587ad496f2a88deaff75cb609f91c
2011-11-30ARM: tegra: power: Save CPU context to non-cacheable stackScott Williams
The standard cpu_suspend does not work if there is an exernal L2 cache in the system individual CPUs are suspending without shutting down the whole CPU complex. As a workaround for this problem, we must save the CPU context to a non-cacheable region of memory. Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
2011-11-30ARM: tegra: power: Fix suspend pgd identity mappingScott Williams
The RAM identity mapping in the suspend pgd was based upon the characteristics of the Tegra2 address map and would not work for Tegra3. Change the mapping so that it's independent of the physical address map characteristics. Change-Id: Ib8f67c169f6b0988e88a4ef7616dfd48e66754ac Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R399b9624e8f25637538273642059e8d0719badf5
2011-11-30ARM: tegra: power: Allocate non-cacheable page for CPU contextScott Williams
The standard cpu_suspend() mechanism doesn't work if there's an L2 cache controller like a PL310 in the system because there's no effective way to flush the saved CPU context out to the L3 memory system. Allocate a page of non-cacheable memory to hold the CPU context. This save area will be utilized in a subsequent change. Change-Id: I1e3bd60bd0bd19c1010905ef65ea0a8597ad6654 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R00d69f8cab6992ed729c1f6ef67fd38c999c3a5b
2011-11-30ARM: tegra: power: Put power functions under CONFIG_PM_SLEEPScott Williams
Place additional functions that are invoked only by code under CONFIG_PM_SLEEP conditionals under CONFIG_PM_SLEEP conditionals also. Change-Id: I224ae07b9031038474b922422422a4feafcd94f1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R65b81ec60f59ae981fd668ad8354b14b8b4c83b9
2011-11-30ARM: tegra: power: Disable power management if pgd alloc failsScott Williams
Disable power management functions if we're unable to obtain memory for our the suspend pgd. Change-Id: If7900535ea05df9441c0b82ccb9152961ea9e12b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R4b616bb53552d2dd8b9da39ca9bc11ad10825f54
2011-11-30ARM: tegra: power: Add debug checks for LP2 entry/exitScott Williams
Add debug traps for recursive attempts to enter or exit LP2 state. Change-Id: I7da05774c90a4fd5b9f2369e801c5b447024698f Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb74239b3fbabf80cf7548c6f5958b0c540ae6b62
2011-11-30ARM: tegra: power: Fix Tegra2 LP2 modeScott Williams
All CPUs are not created equal. CPU0 must be the one to perform the CPU complex suspend actions. CPU complex power gating and rail gating cannot be triggered from CPU1. The Linux 2.6.39 port for Tegra2 violates this hardware restriction. While it may have appeared that the system was entering LP2 state, when entered on CPU1, essentially all that happened was a WFI with no CPU complex power gating and no CPU rail gating. Change-Id: Ie754520264fe8de1b95f523d6575914bf77e747f Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R66e19457bc55bcd84124e3a4e23beae7b4ee707c
2011-11-30ARM: tegra: power: Calculate address of IRAM LP2 mask onceScott Williams
Perform the calcuation of the address of the IRAM copy of the LP2 mask only once because run-time evaluation of it's IO_ADDRESS() is a rather lengthly computation whose value never changes. Change-Id: I8456fa3eb719dcf4f42c360196349177b8907fd9 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R429d76f341410455883ad7d9e28ff66a44eddb98
2011-11-30ARM: tegra: power: Save TWD registers on cluster transitionsScott Williams
The ARM timer/watchdog (TWD) registers do not need saving on LP2 transitions resulting from real idle events. They do still need saving/restoring on transitions resulting from cluster control operations. Change-Id: I459b25b98c256a52a2e9e68fb63dbf2681e90b07 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R3c7c0cae8b847af6355fa1fa0b8bf5bf1e1efef5
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: power: Fix CPU complex suspend/resumeScott Williams
- Invoke cpu_pm_enter()/cpu_pm_exit() to save/restore the GIC processor interface registers for the last processor standing from the cluster control interface. - Disable the GIC processor interface on the last processor standing before shutting down the CPU complex so that wakeup interrupts get routed from the legacy interrupt controller to the flow controller. - For Tegra3 enable GIC pass-through mode to prevent WFI failures. Change-Id: Ia866b17bef47fc8e9e75d4e353394b2d1a09259c Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R249fb53a2622218a7128646d68d8a3552268b4f1
2011-11-30ARM: tegra: power: Fix incorrect flow controller programmingScott Williams
Errors and invalid assumptions about how the flow controller should be programmed were introduced in the port to Linux 2.6.39. - Do not touch the flow controller HALT_EVENTS register for any of the secondary CPUs in suspend_cpu_complex(). Doing so can cause the flow controller state machine to prematurely abort resulting in fatal errors when power gating the CPU complex. - Do not touch the flow controller CSR register for any of the secondary CPUs in restore_cpu_complex(). Doing so can cause the flow controller state machine to prematurely abort resulting in the secondary CPUs waking up before they're supposed to. - suspend_cpu_complex() and restore_cpu_complex() can only be invoked from CPU 0. The hardware does not allow the CPU complex to be suspended from any other CPU. Change-Id: I89546bf53f8f6f12c0e62ce49fc99a46244fa57f Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf61122cb730d852179d8e2d9e667ae7c65b09c58
2011-11-30ARM: tegra: power: Fix TEGRA_SUSPEND_NONE handlingScott Williams
- Do not assert in tegra_pm_set() if the platform suspend mode is set to TEGRA_SUSPEND_NONE. Just return. - Do not override the platform suspend mode to a deeper power saving mode if the SDRAM refresh context save area cannot be obtained. Change-Id: I1ebceef715f9175b8db25af3df28c48582ec0815 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rfe888ac904de11cb5a63475dc95ab736a39f5c4b
2011-11-30ARM: tegra: power: Eliminate extraneous PMC register writesScott Williams
Writes to PMC registers in the 32 KHz domain are extremely slow. Write PMC SCRATCH0/SCRATCH1 regsiters only when entering LP0. Change-Id: Ib85b436330a8a9a0dc7fbc56889a375a534b8d10 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8267387cbe889727ca429c2c6dc44630a061c808
2011-11-30ARM: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets that is copied to IRAM. - Add state information to direct the flow of execution through the reset handler based on the reason a CPU was reset. - Write the EVP CPU reset vector only once per cold/warm boot session. - Prevent modification of the EVP CPU reset vector in Tegra3. Bug 786290 Bug 790458 Change-Id: Ica6707f3514986ee914e73a2d9766a4e06ce2d29 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7b9859a83717e76c3c083bdde724bd5fef9ce089
2011-11-30ARM: tegra: Trivial changesScott Williams
Change-Id: Id45f6be8336370bf011484bea0a90e7e9f49f026 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R06af455b61cb70a1a7dc18b38ad3f816d4ccba63
2011-11-30ARM: tegra: Consolidate flow control registersScott Williams
Change-Id: I07ffcffafcf47fd7539b22d4829712e041293bf3 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R34a7800e24254d54b499411652d59421be703619
2011-11-30ARM: tegra: Rename flow control registersScott Williams
Change-Id: Ibb4f62697819bd3e15164b4e639ff4bc180f92bf Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5d91fec25c89725ed35166dcf3fc3cced3acdc7f
2011-11-30ARM: tegra: Don't die if L2X0 cache is turned offScott Williams
Change-Id: I1e065ae03da74d1ebf3327f8e29df7f81aa512a8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5df55e4c8afeea439ef6003fdf2b89064753bd2
2011-11-30ARM: tegra: Catch early LP2 exitsScott Williams
Change-Id: I107d301ec8e8cd3b69ea293faab15b8d766e38f4 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R9f8f016c1850e2c65f30f2f67241a94acf8a7755
2011-11-30ARM: tegra: Idle event wakeup timerScott Williams
Change-Id: If072ef10f02d5be7560fdf42584ab11b2a863481 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf1ace67e281b1581501aaa936cd9137d326f2c4a
2011-11-30ARM: tegra: Remove LP0/1/2 dependence on CONFIG_SMPScott Williams
LP0/1/2 do not require SMP. Change-Id: I85572da9056a5120c13cd7e65a8062309541b52a Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf20625360cc8926949283b8cb477cf596f7fc3e9
2011-11-30ARM: tegra: Update tegra_lp0_suspend_init stubbingScott Williams
Change-Id: I961125e938e72506dc304025b418e80387a5062e Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R393c5a77803f276467d2974041653eb92026601e
2011-11-30ARM: tegra: Rearrange pm.c for cleaner ifdefsScott Williams
Change-Id: I02a8a10ee842bcc02d590f116484f4ff8d0705b0 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1105e3976f266bf4e229510c8c5ae876f900b2ce
2011-11-30ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
2011-11-30ARM: tegra: Build pm.c even without PM_SLEEPScott Williams
Change-Id: I13799aa03f86c7d83faf8ffa49954fef15aa0bdc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra6e14b10f89a40a1f09169d864dbaa9e62c7280a
2011-11-30ARM: tegra: Make LP2 require CONFIG_PM_SLEEPScott Williams
Change-Id: Iaaf96375eaf7408f5bedc4196d33a04fb94129ef Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R98567e0d894acbdac770b191f7e46f16592d5d0b
2011-11-30ARM: tegra2: Move LP2 into cpuidle-t2.cScott Williams
Move Tegra2 SOC-specific CPU idle functionality to cpuidle-t2.c Change-Id: I26c94ca74d7a78665c52e23571c5058e3da240a7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1246e3942623458f5121ccdac3e6d4a1d40ad624
2011-11-30ARM: tegra: Add cpuidle.hScott Williams
Change-Id: I75ec091f9dcd0fa3fa56b1542f58a02006c1a314 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ree5fce2632aff6dc59879817ad7ad3f2b1538244
2011-11-30ARM: tegra: Finish suspend.h -> pm.h renameScott Williams
Change-Id: Iad4b8a7c73ebe4b23a24b5986807358d481aac55 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rb796a9ffc20dd4fbf9c463bc9cf3c175f4b03f88
2011-11-30ARM: tegra: update copyrightsScott Williams
Change-Id: If50d29696867787b38febd909910dda75475cc30 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2275ad736d4dbee0a7b716ee6ea19b1863d8d4f8
2011-11-30HACK: allow tegra3 compile without SMPDan Willemsen
Rebase-Id: R2f09e8a42a4fe3622924aa66acb13af0bb124e98
2011-11-30get tegra3 compilingDan Willemsen
Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac
2011-11-30fix tegra_cluster_switch compileDan Willemsen
Rebase-Id: R6ebe0a0a67317e00b7cc30d2d2b9485c9c396185
2011-11-30ARM: tegra: power: Restore LP2 in idle protectionsScott Williams
Restore the code that was dropped in the port to Linux 2.6.39 that protects against using LP2 mode for idle when the platform suspend mode has disallowed the use of LP2 mode. Also cleans up some warning messages. Change-Id: I357210b8a272c10bf7c1e773342dc864bbddb74e Reviewed-on: http://git-master/r/40463 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6a60e3f0f2ebf06ec9701475af41679c24ef80ab
2011-11-30ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PMScott Williams
For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration parameter to use on Tegra for power management, and not CONFIG_PM. CONFIG_PM does not have the required dependency on CONFIG_SUSPEND necessary to pull in the CPU suspend/resume functionality used by Tegra. Also fixes compilation errors when CONFIG_PM and by implication CONFIG_PM_SLEEP are not configured. Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad Reviewed-on: http://git-master/r/40458 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
2011-11-30arm: tegra: disable lp0 on tegra3 A01 if it is enabledLuke Huang
Always change to LP1 even if the default is set to LP0 for Tegra3 A01 since LP0 cannot be supported for this chip revision. Bug 789450 782781 Original-Change-Id: I2d62cf458050fcdcdded1fc5bfc08fdb2d09844c Reviewed-on: http://git-master/r/32852 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R904999681a1c35deabb685531843c6c39ba3748e
2011-11-30ARM: tegra: power: Fix warnings when CONFIG_PM is disabledScott Williams
Original-Change-Id: I9d4b8c218cdfe6a91424b808f70c1ec056015783 Reviewed-on: http://git-master/r/32463 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R45bbed19108386e72f1057d09d13290a8bec2c17
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-22 02:38:10 +0000