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The CP14 (debug interface) registers were not being saved as part of
the CPU suspend context. This can cause attached JTAG debuggers to
lose their mind after CPU hotplug or suspend.
Change-Id: Ia9cfd8a711160fd1f0852c33e3fb72f15298de85
Reviewed-on: http://git-master/r/4281
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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in both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely
perform this transition, the final shutdown procedure responsible for
* turning off the MMU and L1 data cache
* putting memory into self-refresh
* setting the DDR pads to the lowest power state
* and turning off PLLs
is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the
start of the suspend process.
in LP1 mode (like LP2), the CPU is reset and executes the code specified
at the EVP reset vector. since SDRAM is in self-refresh, this code must
also be located in IRAM, and it must re-enable DRAM before restoring the
full context. in this implementation, it enables the CPU on PLLP, enables
PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset
vector to restore the rest of the system (MMU, PLLX, coresite, etc.). the
LP2 reset vector is expected to be found in PMC_SCRATCH1, and is
initialized during system-bootup
in LP0 mode, the core voltage domain is also shutoff. as a result, all
of the volatile state in the core voltage domain (e.g., pinmux registers,
clock registers, etc.) must be saved to memory so that it can be restored
after the system resumes. a limited set of wakeups are available from LP0,
and the correct levels for the wakeups must be programmed into the PMC
wakepad configuration register prior to system shutdown. on resume, the
system resets into the boot ROM, and the boot ROM restores SDRAM and other
system state using values saved during kernel initialization in the PMC
scratch registers
for simplicity, the outer cache is shutdown for both LP0 and LP1; it
is possible to optimize the LP1 routine to bypass outer cache shutdown
and restart
v2 fixes from Vik Kasivajhula:
* restore PLLC during LP1 resume
* fix typo which set the CPU clock burst policy to PLLM, rather than PLLP
Change-Id: Icb1d2cbcbac8503369a10d16fd5c8b561af5a35a
Reviewed-on: http://git-master/r/1773
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
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Added support for wake event delay, and CPU power off time controls.
Exposed the respective settings as ODM PMU properties.
Bug 690326.
Change-Id: I2c30365de3fce4e2d45b1e66c7af9087f10d8451
Reviewed-on: http://git-master/r/2377
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
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implement basic support for system suspend operations using LP2 (CPU
power-gating)
platform-specific data (power good times, PMU capabilities, etc.) must be
specified when registering the suspend operations, and a helper function
for mapping from wakeup pad and PMU property data from the ODM kit to
the platform_data structure is provided.
AVP & RM suspend is performed in the prepare_late callback, ensuring that
these operations are executed after all drivers have suspended, to eliminate
ordering conflicts on RM dependencies
since all device interrupts (except timers) are disabled in the suspend
path, the wakeup interrupts need to be manually unmasked before entering
into a suspend state or the processor will never wake up; these forced-unmask
interrupts are re-masked immediately in the resume path to prevent the
kernel from live-locking prior to driver resume.
Change-Id: Ibe4d594d450b253744d803a0a15d66ae275029e8
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LP2 idle mode power-gates the main CPU complex, requiring a
full processor state save and restore from a reset vector
processor context area is allocated during platform initialization
from the kernel, and mapped into the hotplug page tables (which also
serve as the initial page tables for the LP2 main processor reset)
restoring the processor from LP2 requires calculation of a system-
and APB-clock-dependent CPU power good timer value. on Harmony,
2ms is a good baseline value for this, and the APB clock is running at
13.5MHz. these values need to be un-hardcoded for other platforms.
Change-Id: I70a18a1d995e1d34da64d60fbdcd4568ef442f0c
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