Age | Commit message (Collapse) | Author |
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Integrate ADV7180 and MAX9526 video decoder support and prepare for
drivers as modules.
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Export tegra_powergate_is_powered() for use by modules.
Change-Id: I8cfbb8aeb95dca00cbf6ef0c8c2bd189afeb62b6
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/97724
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Add a trace event for powergating. The existing power_domain_target is used.
state 0 is used for off and state 1 is used for on. This patch only traces
non CPU domains. The powerstate of CPU domains is already traced using
power_start events.
bug 976845
Change-Id: Ic9503f7b42b35c0bf70c7b64a7f15c4960637200
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/99416
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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All these clock operations should be handled by
powergate operations.
bug 840051
Reviewed-on: http://git-master/r/66177
(cherry picked from commit 1ad8fe3e184db04063275c837e240827bda009e9)
Change-Id: I0159c6c1f64932b22b25d31d4bb1ff9d41385879
Reviewed-on: http://git-master/r/86126
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
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Client list for TEGRA_POWERGATE_HEG was not padded with MC_CLIENT_LAST,
which causes an infinite loop if HEG is power gated.
Bug 855755
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/62129
(cherry picked from commit b36a3ef9584ceb23bd0ed97ba662a12ec08ce957)
Change-Id: Id6ad765db682ee153c7a271e01e3c40e462db6c4
Reviewed-on: http://git-master/r/67126
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Fixes the return value for tegra_powergate_set () when new status
to be set and current status are same.
Change-Id: Iffbc4fac239c4ea21f3026cbf33fe4fb7941aa2d
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/66404
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/51157
Rebase-Id: R795bf03590a76b6c494afd37603ed951dc2cd082
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Clean up conditionals.
Use the generic name of CELP for the LP partition.
Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a
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Bug 857044
Original-Change-Id: I80c8c2183426fbaa8b7d5316c09709c9de7ea39d
Reviewed-on: http://git-master/r/45970
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rd8c46b56d4ca22e05e40c664329d64f7bd6710f7
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Add support for resetting a module.
Bug 625545
Original-Change-Id: Ibc5e57d73085e85f3d1184d0657d9bc650b28e4e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/46870
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rcaa388b315159b1cc69dd29dd03176f4136bd285
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Enable sata rails and sata partition when driver initializes
- add sata_oob and cml1 clocks to sata powergate partition.
- set sata and sata_oob clock source using clk_set_parent API.
- fix a bug in while(timeout) loop
Bug 836589
Original-Change-Id: Iddc08bf851ffc83d45bd6aed4df85cde3b13f0e4
Reviewed-on: http://git-master/r/41314
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R500e99ac50d1e3c0851958b1c83316dded00d617
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By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions. Also
3D,3D1 and MPE are not powergated at startup.
Original-Change-Id: Ibc74868eb59af7c0e8b5a1ecd78e6f993dd5d3a6
Reviewed-on: http://git-master/r/35955
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Ra55d87d7d816d7cf0bea0d28e7865fa7760f869f
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This change provides a centralized location for powergating modules.
It would take care of switching on/off clocks while un-powergating/
powergating modules respectively.
Bug: 814267
Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710
Reviewed-on: http://git-master/r/31776
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Rc0aac0edd4e693c15d22d998c882fceeeb85765d
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Fixed non-Boolean return value in tegra_powergate_is_powered().
Change-Id: I3ae058d290bc288d24e66d7b78cf2338266e6723
Reviewed-on: http://git-master/r/40466
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R2492cc7a0f25bcb00376147dc3ffc542a89e2e89
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Change-Id: I6dbc601cde3297e7c6fd63600c588cb3774271b8
Reviewed-on: http://git-master/r/35940
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: R18e4758ac88779a5f21c5c1a01663f08bcc35a1f
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Original-Change-Id: I0e37b788c666ae99f46e7e6995c3700b0b23d412
Reviewed-on: http://git-master/r/29901
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R24afa8e7f33265722cee139f37ad53774d1dcb96
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Original-Change-Id: Ie4b29d1119bc2f640891525ab781c8de1bf64ddf
Reviewed-on: http://git-master/r/23215
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idc616485ecdb9e7c39728409d91a511e1de79e05
Rebase-Id: Rd61725b233749ea76467686439b92ac22b65f424
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The PCIE and VDE power gated controls are not swapped on just
Tegra2. The swapping has been enshrined as a "feature" now.
Original-Change-Id: Iad8820570414d5377d9d6eed65a57190c4eaec7f
Reviewed-on: http://git-master/r/14000
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ieb72637c659ca05ff1a3b2c363e2d76a66f48ad8
Rebase-Id: R2c55a9fc3c44526a786aaf80fb57d7dd29b12cdc
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Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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Change-Id: Iff865e0f74e1667aa6e998a63d33d3b4cd09694c
Signed-off-by: Benoit Goby <benoit@android.com>
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Allow calling tegra_powergate_sequence_power_up on a partition
that is already powered. Reset the partition, and return success
with the clock enabled.
Change-Id: I776c6a84091f0bb8faca22d87b3fabf0cfede564
Signed-off-by: Colin Cross <ccross@android.com>
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Signed-off-by: Colin Cross <ccross@android.com>
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