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2012-11-27tegra: fix file names and paths in commentsMarcel Ziswiler
Several file names and paths showed copy/paste or otherwise issues.
2012-08-29arm: tegra: Set Core to 0.95V in LP1Karthik Ramakrishnan
When the device prepares for LP1, the Core voltage is set to the highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and Cardhu). This is to set for some of the driver suspend along the sequence need a higher emc frequency and thus a higher Core voltage. Since the sequence of drivers suspend depends on the sequence of their registration in the table, which in turn is platform-dependent, there is no right place in the LP1 entry path where the Core voltage can be set to a lower voltage. Hence, the Core voltage remains high in LP1 resulting in higher power. Thus, the only safe location where the Core voltage can be lowered is once all the drivers are suspended and the DRAM is set in self-refresh, at the final point just before the system is suspended in the IRAM code. This location at the assembly code ensures that no other module will be running and thus that nothing will require a higher core voltage. The Core is set to the lowest possible value since nothing requires it. It is then restored to the highest voltage as soon as the LP1 resume code is started so that all drivers are resumed safely. At the execution point in IRAM during LP1 suspend path, even the I2C clocks are gated. They must be reset first and then the I2C transaction is performed. An I2C transaction involves 4 bytes of data, to send the slave address, the Core voltage register address and 2 bytes of data which has the value to set the voltage(the second byte is not required for this transaction). Once these registers are set, the I2C transaction is performed by setting the I2C transaction register to 0xA02. After sending the I2C transaction, we wait for about 250us to check the status of the transaction and if not updated, wait for more time to check again. If after 2ms and the transaction fails to register, the transaction is aborted and the device is allowed to enter at high voltage. Since the failure rate of I2C transaction is very low at this point in execution where there will be no conflicts in the bus, it is okay to have Core high for some of the LP1 cycles. However, it is unacceptable for the I2C transaction to fail on the way from LP1 resume since the device cannot come up with a lower Core voltage. In this case, the transaction is retried again and again till it is successful. There is no way but to keep trying as the device would fail to resume with Core at 0.95V. Each platform(or each PMU) has different values for the I2C transaction ie. slave address, Core voltage register and the value to set the voltage. For the device in IRAM, it cannot access anything in SDRAM memory, these values needs to be pushed to IRAM memory before the device starts execution in IRAM. This is done during initialization of suspend code when it picks values from the board files and copies it to IRAM part of code, before the whole memory is copied to IRAM. This new feature is controlled by a KConfig variable TEGRA_LP1_950 which should be enabled once the board file of the device is updated with the right values. The device hangs when it does not have the right values for the I2C transaction. With this change in Core, LP1 power is reduced by 12mW in Enterprise, 20mW in AP37 and about 24mW in Kai. Bug 1035684 Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com> (cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296) Reviewed-on: http://git-master/r/124779 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-07-13ARM: tegra: clock: Allow Tegra3 PLLM rate changeAlex Frid
Allowed Tegra3 memory PLLM rate change, provided it is disabled. Since PLLM can deviate from boot configuration now, and on Tegra3 it is controlled by PMC override registers (not CAR module registers): - Re-factored PLLM initialization, resume, and set rate operations accordingly (enable and disable ops already used PMC override). - Made sure that boot configuration is restored on entry to LP0 to match memory timing saved in scratch registers. Bug 1005576 Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110937 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8) Reviewed-on: http://git-master/r/114759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-04-19Revert "ARM: tegra: rethink the cpu suspend-resume code path"Sang-Hun Lee
This reverts commit f31ca2d9e0580b58dc51fde31fc8ace190dd253b. Bug 967887 Change-Id: I3fe975f7a6939cace5e208947bcb82e09008c0ac Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96787 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU"Sang-Hun Lee
This reverts commit 743c03fbeb5908faf4aef6bee7702a2ad4caac22. Bug 967887 Change-Id: Ie4477e3b5fa9773c9e60b5cace47b3ff240a4bf1 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/96785 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPUVarun Wadekar
Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/92542 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-05ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/84481 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-04-05arm: tegra: turn off pll-a/p in LP1Mayuresh Kulkarni
- current code does not turn off pll-a/p in LP1 irrespective of voice call status - add a new flag to indicate voice call on-going - use PMC_SCRATCH37 to hold this flag - if it is set, do not turn-off pll-a/p during LP1 - save-restore PMC_SCRATCH37 if it was used to hold the voice call on-going flag - fix few misc formatting issues in tegra3_cpu_clk32k Bug 924817 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/85768 (cherry picked from commit 7853981c987ae329620bb54d869016cb74a6c054) Change-Id: Id5348d2eb44a4bacaf00f6d17edceedaef819e29 Reviewed-on: http://git-master/r/94395 Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-23ARM: tegra: power: Don't lower clocks on LP0 entryAlex Frid
Do not change (lower) CPU and system clocks, and do not disable PLLs on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1) Change-Id: I2f175882d4d3dcfe5aee9c460f873a5e907e4ece Reviewed-on: http://git-master/r/84714 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2011-12-22arm: tegra: pm: do not turn off PLL-P & PLL-A for LP1 on Tegra3Nikesh Oswal
Bug: 917672 Change-Id: Ie3446f7fdaa05a6dab43375b842b37070cea33b7 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/71173 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
2011-12-15ARM: tegra: clock: Use Tegra3 PLL lock indicatorsAlex Frid
Bug 873599 Change-Id: Ice84a63d90d39105e53505282fe126e56c4749db Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/68897 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-12-08arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30ARM: tegra: power: Correct EMC_ADR_CFG maskDaniel Solomon
The mask used to check bit EMEM_NUMDEV in register EMC_ADR_CFG is wrong for T30. Correct it. Change-Id: I3deb1229cb27081049de1a4f2fd69e21507fa853 Reviewed-on: http://git-master/r/65927 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R328e76d0f107d1b2fe1f27a81c1fab82dc4808d6
2011-11-30ARM: tegra: power: Do not switch Tegra3 to PLLPAlex Frid
Do not switch Tegra3 to PLLP on sleep entry: no need - unlike Tegra2 PLLX on Tegra3 is not disabled when CPU is rail gated; also G/LP mode switch clock configuration is set by mode switch prolog and should not be overwritten at the last moment. Change-Id: I9aa8463c6b1c04c0a70e70c1e2cd4113a679e100 Reviewed-on: http://git-master/r/57202 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R9a8d78a363c261d45e48832fcbed7fa2854f7da8
2011-11-30arm: tegra: correcting wfi sequencevenu byravarasu
As per hardware documentation, dsb should precede wfi. Hence fixing it. Change-Id: I1c98581dfe3891d425ab36c1a2bb313e19ad046d Reviewed-on: http://git-master/r/54626 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R3d7e46306d7d97c2cdfa0ec7ce658a1658724a76
2011-11-30ARM: tegra: power: fix lp0 suspendJin Qian
enable pllm and skip io_dpd for lp0 Bug 862504 Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7 Reviewed-on: http://git-master/r/50239 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0
2011-11-30ARM: tegra: power: implement LP1 suspend/resume for Tegra3Yudong Tan
Bug 862502 Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722 Reviewed-on: http://git-master/r/47398 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef
2011-11-30ARM: tegra: power: Use uniform save/restore register setScott Williams
Modify the register usage of tegra_cpu_save so that the same set of registers is saved to and restored from the stack. Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
2011-11-30ARM: tegra: power: Consolidate CPU context save and SMP exitScott Williams
Every call to tegra_cpu_save is always followed by a call to tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save by folding the CPU context save functionality of cpu_suspend and the coherency exit functionality into a single function called tegra_cpu_suspend. Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8
2011-11-30ARM: tegra: power: Delete obsolete functionScott Williams
Deleted tegra3_sleep_cpu which is never called by anything. Change-Id: I59a737e92ed8bec222cec65252cc19592e171fd6 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R1fabb1b9a728f1d4ff99643b4d31cfe7292c260d
2011-11-30ARM: tegra: power: Add LP2 in idle support for secondary CPUsScott Williams
Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917
2011-11-30ARM: tegra: power: Split CPU context save and coherency exitScott Williams
Separate the CPU context save and CPU coherency exit into separate functions. Change-Id: I7c5376677e293342b02b5bebdef6be2610522936 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d
2011-11-30ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2011-11-30ARM: tegra: Add Tegra 3 CPU hotplug supportScott Williams
Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341
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