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use buffered memory to bypass L2
add memory barrier after cpu suspend
Bug 862494
Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe
Reviewed-on: http://git-master/r/47172
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7
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Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84
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The common ARM CPU state suspend/resume code does not work with
and external L2 cache controller (like a PL310) enabled. This
change fixes corruption of the current PMD by the MMU resume code.
cpu_resume_mmu modifies the currently active page tables to add
a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to
handle MMU off-to-on transition. It turns off the L1 data cache
but it knows nothing of the L2 cache. Since page table walks are
L2 cacheable, other CPUs in the system can pick up the corrupted
PMD which will eventually result in a kernel panic.
The workaround for this is to modify push_ctx_regs to save the
current TTB0 and CONTEXID registers in the CPU register context
and switch to the private tegra_pgd before saving the rest of the
CPU context. The tegra_pgd already has a flat mapping for the
code in question, so it can't be damaged by the actions of
cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore
the actual TTB0 and CONTEXTID registers when restoring the CPU
registers.
Change-Id: Ided2b31cbea0b0abb934e64cf056e85e1a3f06ae
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R3f6ca9c63752430395fdf8375b82794abc9776af
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The standard cpu_suspend does not work if there is an exernal
L2 cache in the system individual CPUs are suspending without
shutting down the whole CPU complex. As a workaround for this
problem, we must save the CPU context to a non-cacheable region
of memory.
Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
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Tag the stack frame created by the CPU register context push
macro with a magic number and validate that magic number in
the register context pop macro to ensure that the stack
remains balanced and uncorrupted.
Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60
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Define macros to ensure that the behavior of push/pop of the
context regsiter set is consistent across all callers.
Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4
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Modify the register usage of tegra_cpu_save so that the same set
of registers is saved to and restored from the stack.
Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
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Change-Id: Ie2f619df4e5bff06960dcaa910a39d4cff78b879
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Ra75a8dba9e8f0fa57081a3fed9b3ef743b3c8796
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Every call to tegra_cpu_save is always followed by a call to
tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save
by folding the CPU context save functionality of cpu_suspend and
the coherency exit functionality into a single function called
tegra_cpu_suspend.
Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8
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Define the SMP coherency exit code as a macro to allow it to be
inlined in assembly code that needs to control its register usage.
Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a
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Clean up some rather fragile manipulation of the stack pointer in
the CPU suspend code. It's all unnecssary except in one case where
Tegra2 can abort a suspend because of activity on the other CPU.
Change-Id: Ic872364c5abd58f704b2afeeae4d8722f127d3bb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R5873dd120df2e98cc5bfcc74f86ebea6cc10f9b2
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Separate the CPU context save and CPU coherency exit into separate
functions.
Change-Id: I7c5376677e293342b02b5bebdef6be2610522936
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d
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Add support for forced Tegra3 LP2 low power mode on the boot processor
(CPU 0) via the cluster control interface when all others are offline.
Switching to the LP CPU mode is also enabled with this change.
LP2 in idle and LP2 mode on the secondary processors is not yet
supported.
Change-Id: Icb898729f093be5e006c413f701532dd45228687
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
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The MMU shutdown code must be aligned to an L1 cache line boundary.
Change-Id: Ib6c976470983b7f69b45e720104fc65cae54e162
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R305325117ba1debc8d112b4c3596c158df98d75e
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Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516
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Decouple LP3 (WFI) mode and CPU hotplug shutdown from CONFIG_PM_SLEEP.
Change-Id: Ie959fa5e044ab4a7f84772d3b743ce2680465acc
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R8f01e646e7bf65350db44557de87c4c2a33d8059
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Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
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Removed unnecessary barriers by removing the read-back of the flow
controller halt register. The delay caused by the readback gets
worse as the number of cores increase. By using raw writes instead,
page fault handler performance improves siginificantly.
In addition, the flow controller CSR interrupt and event status is
cleared to ensure proper operation on Tegra3.
Change-Id: I92d0a1487a16c39438038b9bfff591bc69195ab8
Reviewed-on: http://git-master/r/40461
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R98ecb17b3cdec99f69f7067ec7bdd7b00d789da9
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The movw/movt instruction pair (encapsulated by the mov32 macro)
is preferred over literals for loading addresses. The use of literals
for singleton data accesses can cause unnecessary cache misses and
evictions for cache lines that are unlikely to be accessed again in
the near future. Furthermore, certain code sequences must refrain
from using data accesses. Therefore, in general, addresses should
be loaded by mov32.
Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a
Reviewed-on: http://git-master/r/40460
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
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tegra_sleep_wfi disables coherency to prepare for possibly
resetting the cpu. If an interrupt is received, it exits
wfi and re-enables coherency, but it was not flushing the
tlbs or the branch predictor array, which could have been
updated by broadcast tlb operations that were ignored.
Flush the tlbs and branch predictor array when exiting.
Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191
Signed-off-by: Colin Cross <ccross@android.com>
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Tegra supports three low power modes that involve powering down the CPU.
LP2 powers down both CPU cores and the GICs, but leaves the core
peripherals, including the memory controller and the legacy
interrupt controller, enabled. The legacy interrupt controller
is used as the wakeup source, and any interrupt can wake the device.
LP2 can be used in idle.
LP1 is the same as LP2, but in addition turns off the memory
controller and puts the DDR memory in self-refresh. Any interrupt
can wake the device. LP1 could be used in idle if no peripherals
are doing DMA.
LP0 turns off everything in the SoC except the RTC and a power
management controller, both of which run off a 32 kHz clock.
The power management controller has 32 wake sources, all other
interrupts can not be used to wake from LP0.
These low power modes power-gate the main CPU complex, requiring a
full processor state save and restore from a reset vector.
Platform-specific data (power good times, PMU capabilities, etc.) must be
specified when registering the suspend operations to ensure that platform
power sequencing restrictions are maintained.
In both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely
perform this transition, the final shutdown procedure responsible for
* turning off the MMU and L1 data cache
* putting memory into self-refresh
* setting the DDR pads to the lowest power state
* and turning off PLLs
is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the
start of the suspend process.
In LP1 mode (like LP2), the CPU is reset and executes the code specified
at the EVP reset vector. Since SDRAM is in self-refresh, this code must
also be located in IRAM, and it must re-enable DRAM before restoring the
full context. In this implementation, it enables the CPU on PLLP, enables
PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset
vector to restore the rest of the system (MMU, PLLX, coresite, etc.). The
LP2 reset vector is expected to be found in PMC_SCRATCH1, and is
initialized during system-bootup.
In LP0 mode, the core voltage domain is also shutoff. As a result, all
of the volatile state in the core voltage domain (e.g., pinmux registers,
clock registers, etc.) must be saved to memory so that it can be restored
after the system resumes. A limited set of wakeups are available from LP0,
and the correct levels for the wakeups must be programmed into the PMC
wakepad configuration register prior to system shutdown. On resume, the
system resets into the boot ROM, and the boot ROM restores SDRAM and other
system state using values saved during kernel initialization in the PMC
scratch registers.
Resuming from LP0 requires the boot ROM to supply a signed recovery codeblob
to the kernel; the kernel expects that the length and address of this blob
is supplied with the lp0_vec= command line argument; if not present, suspend-
to-LP0 will be disabled
For simplicity, the outer cache is shutdown for both LP0 and LP1; it
is possible to optimize the LP1 routine to bypass outer cache shutdown
and restart.
Includes fixes from:
Scott Williams <scwilliams@nvidia.com>
Aleksandr Frid <afrid@nvidia.com>
Vik Kasivajhula <tkasivajhula@nvidia.com>
Bharat Nihalani <Kbnihalani@nvidia.com>
James Wylder <james.wylder@motorola.com>
Allen Martin <amartin@nvidia.com>
Change-Id: I9e4e61c2fbb8c7bb5a29b1832ea38e7ea0524c52
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
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