summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/sleep.S
AgeCommit message (Collapse)Author
2013-04-22ARM: tegra114: Implement ARM errata 799270 properlyBo Yan
The ARM errata 799270 requires a data dependency between the returning device load data and MCR instruction that sets ACTLR.SMP bit. Fix the current workaround so it confirms to errata document. bug 1195192 Change-Id: Ideeb3dd3d865323d59ae4bc7a2d40889acfe379d Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/211812 (cherry picked from commit 6b738d1059962d80857b09d70a8878915f17c39e) Reviewed-on: http://git-master/r/221142 GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-by: Ankit Pashiney <apashiney@nvidia.com>
2013-01-30ARM: tegra: Add barriers after cache operationsAmit Kamath
memory and instruction barriers are needed after the tlb is invalidated and BTAC is flushed as per ARM TRM. Without this there is a invalid page translation in some cases. Bug 1189280 Change-Id: I85e297ffd9245c5066f656bbb70ea257b8b3b317 Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/195070 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
2013-01-24ARM: tegra11x: Fix BOND_OUT_L accessAntti P Miettinen
Fix BOND_OUT_L register access to use the right offset. Change-Id: I0ccc2adc6aaef7e542436e2c4d65994c59a5a2d3 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/192407 (cherry picked from commit 4d4758c45e5f330ebedf1b6417af98fc85682c78) Reviewed-on: http://git-master/r/193321 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
2013-01-15secureos: tegra: Remove duplicated L2 cache flushHyung Taek Ryoo
This change removes deplicated L2 cache flush. Moves SMC(0xFFFFFFE4) a bit later in the PM entry process, replacing tegra_flush_cache in tegra_sleep_cpu_finish(). Bug 1195365 Change-Id: Id52ab4963a955fa1b1e069d132873a4d9d902518 Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com> Reviewed-on: http://git-master/r/190431 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
2013-01-10ARM: tegra11x: start L2 clock before enabling SMPBo Yan
Do an external device read to start L2 clock, then change SMP bit in ACTLR. The ACTLR change needs to be done immediately after the device read is done since there are only 256 clock cycles maximum available before the L2 clock can be gated again. bug 1208654 bug 1195192 Change-Id: Ide1c0476d629cbea07f585013ed3b7e79a67c86e Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/189712 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
2012-10-29ARM: tegra: replace tegra_cpu_wfi with cpu_do_idleBo Yan
Function "cpu_do_idle" is defined in ARM common code, there is no need for "tegra_cpu_wfi" which has the identical implementation. Change-Id: I8ca3ada171990148162276a76434aebd2bd188e2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/159157 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-10-21Revert "arm: tegra: optimize L2 enable/disable paths for secureos"Deepak Nibade
With this revert, Dalmore enters LP0 state in Main Otherwise NULL exception is encountered (variable l2x0_base) Revert is required till we get proper secureos code and we ensure that T114 does not enter l2x0 code This reverts commit 7274dfdea8e1512b863438d4f34074a67b5b4a97. Change-Id: Ib3ff4f1664fdc1693c2768eb3ecc0205a456c982 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/145288 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-10-10ARM: tegra: cluster switch for T11xBo Yan
1. for secondary CPU, always flush L1 only, this is irrespective of Cortex A9 or Cortex A15 2. disable cache before flushing it when rail-gating CPU0 3. do not flush cache before entering ARM common code cpu_suspend, which by itself will flush cache. Still, it's highly desirable to flush cache in __cpu_suspend_save, since this will flush L2 irrespective of A9 or A15. Reviewed-on: http://git-master/r/133945 Change-Id: I2c6eb20546b5fc8b5432dc73c2f97480cbf29ee8 Signed-off-by: Bo Yan <byan@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143126 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-09-27ARM: Tegra: Move cache disable to flush functionAntti P Miettinen
During power gating we need to make sure that all state is properly flushed to ungated part of the chip. To ensure that data cache is completely cleaned after flush, the cache needs to be disabled before flush. When data cache is disabled we naturally cannot write to cacheable memory. Therefore handle the disable inside the flush function. Bug 1045096 Change-Id: I740ffdfd43c4b75bf58aaad4279092040a8c7405 Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com> Reviewed-on: http://git-master/r/133799 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-09-26arm: tegra: optimize L2 enable/disable paths for secureosVarun Wadekar
For the CONFIG_TRUSTED_FOUNDATION code paths, differentiate L2 enable vs. reenable, which are different SMCs (won't trigger an invalidate in the case of a reenable). On an L2 disable SMC, optionally pass a 0 for the L2 ways arg, which skips the full clean/invalidate (and simply just disabled the L2). In order to safely skip flushing the L2 on the disable, we have to be careful what we dirty from the type we flush the L1 and disable the L2. Reviewed-on: http://git-master/r/119786 Original-author: Chris Johnson <cwj@nvidia.com> Change-Id: Iebcf1042ce2b58513e40e9d49f87ecec9dfdd301 Signed-off-by: Chris Johnson <cwj@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/130061 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-28ARM: tegra11: Update cache flush/invalidate for power gatingBo Yan
The field ENABLE_EXT in CSR register controls what power partition to be gated. If it's CPU-partition power gating only, there is no need to flush or invalidate L2 cache before/after power gating. With this change, L2 cache is flushed/invalidated only when the non-CPU partition is to be power gated or when rail gating is selected. Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/103476 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-06-28ARM: tegra: implement L1 cache flush functionBo Yan
The function flush_cache_all flushes all caches within level of coherency. For CortexA9, this is ok since only L1 is defined. For CortexA15, it will flush both L1 and L2, this behavior is not desired when there is no need to touch L2. So a new function is defined to just flush L1 cache. Change-Id: Id5a651770b70496d0dde6e90b226a19df90a57d0 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/102682 Reviewed-by: Mark Stadler <mastadler@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-24tegra:cpuidle:remove flow-controller programmingPrashant Gaikwad
bug 937980 Remove some legacy flow-controller programming from LP3 entry and exit paths. Also remove data synchronization barrier instruction after wfi to improve scaling across cores. Signed-off-by: satya popuri <spopuri@nvidia.com> Reviewed-on: http://git-master/r/86451 (cherry picked from commit f88ee65418126365fc10af3d3771bba5d2e41d57) Conflicts: arch/arm/mach-tegra/sleep.S Change-Id: I26d700c4bc0ed73e5fed528be524b3d04226f8af Reviewed-on: http://git-master/r/104375 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-09ARM: tegra: sleep: remove <asm/system.h>Varun Wadekar
Change-Id: I72829dbf97952f252e0db9f02381b4412f1e85e5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-07Merge branch '3.4-rc1' into android-tegra-nv-3.3-rebasedVarun Wadekar
Change-Id: Ib3b69ffc5ac3e07c9cc44cc49e9142088eec477e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-27ARM: tegra: rethink the cpu suspend-resume code pathVarun Wadekar
The current kernel methodology expects that tegra_cpu_suspend is actually the last function in the entire suspend sequence. In order to achieve this, the code needs to be remodelled a bit so that we actually execute native cpu_suspend at the end of the suspend sequence. This allows us to leverage all the cpu_suspend code developed by ARM in the upstream kernels. Bug 934368 Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-27ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPENDVarun Wadekar
Bug 934368 Change-Id: Ic9d75cbb0c324b1858b2e476e33dd4f96349bce3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-27Revert "ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu"Dan Willemsen
This reverts commit 48565a367997c1748c655bc834e06b348d4e5b2c. Change-Id: I0e1411f1260ae916c510478276d88b41416a0d42 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-23arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R57977499bb6b372ac4faa360e442e8733265e9f3
2012-03-22ARM: tegra: power: Fix build error on non-SMP systemsScott Williams
Can't use NR_CPUS on non-SMP systems. Just use the maximum. Change-Id: I00b455adf950869146dfcd176efe4abdbe7aa24e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/87416 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Rd38f56587bd586144b67680d3e6c595d5f6b3def
2012-03-22tegra: cpuidle: remove flow-controller programmingsatya popuri
bug 937980 Remove some legacy flow-controller programming from LP3 entry and exit paths. Also remove data synchronization barrier instruction after wfi to improve scaling across cores. Signed-off-by: satya popuri <spopuri@nvidia.com> Reviewed-on: http://git-master/r/86451 (cherry picked from commit f88ee65418126365fc10af3d3771bba5d2e41d57) Change-Id: I7bca4328044ef477bc4bec9c9af9d30d8815d6ce Reviewed-on: http://git-master/r/87212 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Satya Popuri <spopuri@nvidia.com> Rebase-Id: R017b9cf3d72b1f09be6ff339dafd102829edcadf
2012-03-22ARM: tegra: copy native ARM code behavior for cpu suspend-resumeVarun Wadekar
The cpu suspend-resume code now duplicates the non-tegra part from the native ARM code. Bug 934368 Change-Id: I100c8de8e107d1baebb6ec30a1f6f77bca8f44aa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/83098 Rebase-Id: R84c5cc310386966c4f31e1149c9065602d1bc1ef
2012-03-22arm: tegra: pm: preserve r4 - r11 across a suspendVarun Wadekar
Make cpu_suspend()..return function preserve r4 to r11 across a suspend cycle. This is in preparation of relieving platform support code from this task. Original commit: 5fa94c812c0001ac7c3d8868e956ec514734a352 Bug 911002 Change-Id: If33c32ba7de449288eac8f83cb0898ba77a46333 Acked-by: Frank Hofmann <frank.hofmann@tomtom.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R79c9865c168b8fde6a02b1ddce1bd98400e19161
2012-03-22arm: tegra: pm: move return address (for cpu_resume) to top of stackVarun Wadekar
Move the return address for cpu_resume to the top of stack so that cpu_resume looks more like a normal function. Original commit: 2fefbcd58590cf33189c6178098e12b31b994b5f Bug 911002 Change-Id: I275930306a3b4ecb551a32da5f9f26dba53459ec Acked-by: Frank Hofmann <frank.hofmann@tomtom.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R54ebcedde6a84a538f44bcec759af88fef0abe4c
2012-03-22ARM: tegra: power: L2 cache sync only for CPU0 LP2Prashant Gaikwad
Bug 901430 Bug 905813 Change-Id: Id57f870262eebe6a2017b808d1a66624f903989d Reviewed-on: http://git-master/r/64103 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc3cad5fafa9e62fa10099bc4dc1281954a04b8f5
2012-03-22ARM: tegra: power: Correct PL310 virt addr calculationPuneet Saxena
PL310 virtual address was calculated using PPSB virtual/phy address. It should be done using CPU virtual/phy address. This causes TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's Vmalloc region on whistler. Bug 881831 Bug 867094 Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/62097 Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f
2012-03-22ARM: tegra: power: Fix build error on non-SMP systemsScott Williams
Can't use NR_CPUS on non-SMP systems. Just use the maximum. Change-Id: Ie0d6289c3b8bdaada6335e4670c9f6b5ab2bcc93 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49344 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R58abf556bf542b8cf0ee6dd0f091806235f49623
2012-03-22ARM: tegra: Fix build errors when PM_SLEEP is not selectedScott Williams
Change-Id: I2037be4b1309ac1fe9af0ec3e644e0a1a4924857 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/48796 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R0840ee98b17984f73f9a5396ab6f86d4d92b744e
2012-03-22ARM: tegra: power: use buffered memory for suspend contextJin Qian
use buffered memory to bypass L2 add memory barrier after cpu suspend Bug 862494 Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe Reviewed-on: http://git-master/r/47172 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7
2012-03-22ARM: tegra: power: Perform L2 cache sync when flushing L1Scott Williams
Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84
2012-03-22ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmuScott Williams
The common ARM CPU state suspend/resume code does not work with and external L2 cache controller (like a PL310) enabled. This change fixes corruption of the current PMD by the MMU resume code. cpu_resume_mmu modifies the currently active page tables to add a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to handle MMU off-to-on transition. It turns off the L1 data cache but it knows nothing of the L2 cache. Since page table walks are L2 cacheable, other CPUs in the system can pick up the corrupted PMD which will eventually result in a kernel panic. The workaround for this is to modify push_ctx_regs to save the current TTB0 and CONTEXID registers in the CPU register context and switch to the private tegra_pgd before saving the rest of the CPU context. The tegra_pgd already has a flat mapping for the code in question, so it can't be damaged by the actions of cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore the actual TTB0 and CONTEXTID registers when restoring the CPU registers. Change-Id: Ided2b31cbea0b0abb934e64cf056e85e1a3f06ae Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R3f6ca9c63752430395fdf8375b82794abc9776af
2012-03-22ARM: tegra: power: Save CPU context to non-cacheable stackScott Williams
The standard cpu_suspend does not work if there is an exernal L2 cache in the system individual CPUs are suspending without shutting down the whole CPU complex. As a workaround for this problem, we must save the CPU context to a non-cacheable region of memory. Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
2012-03-22ARM: tegra: power: Add stack frame debug checksScott Williams
Tag the stack frame created by the CPU register context push macro with a magic number and validate that magic number in the register context pop macro to ensure that the stack remains balanced and uncorrupted. Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60
2012-03-22ARM: tegra: power: Define push/pop context register macrosScott Williams
Define macros to ensure that the behavior of push/pop of the context regsiter set is consistent across all callers. Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4
2012-03-22ARM: tegra: power: Use uniform save/restore register setScott Williams
Modify the register usage of tegra_cpu_save so that the same set of registers is saved to and restored from the stack. Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
2012-03-22ARM: tegra: power: Use standard definitions for SCTLRScott Williams
Change-Id: Ie2f619df4e5bff06960dcaa910a39d4cff78b879 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Ra75a8dba9e8f0fa57081a3fed9b3ef743b3c8796
2012-03-22ARM: tegra: power: Consolidate CPU context save and SMP exitScott Williams
Every call to tegra_cpu_save is always followed by a call to tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save by folding the CPU context save functionality of cpu_suspend and the coherency exit functionality into a single function called tegra_cpu_suspend. Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8
2012-03-22ARM: tegra: power: Add SMP coherency exit macroScott Williams
Define the SMP coherency exit code as a macro to allow it to be inlined in assembly code that needs to control its register usage. Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a
2012-03-22ARM: tegra: power: Clean up stack pointer handlingScott Williams
Clean up some rather fragile manipulation of the stack pointer in the CPU suspend code. It's all unnecssary except in one case where Tegra2 can abort a suspend because of activity on the other CPU. Change-Id: Ic872364c5abd58f704b2afeeae4d8722f127d3bb Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5873dd120df2e98cc5bfcc74f86ebea6cc10f9b2
2012-03-22ARM: tegra: power: Split CPU context save and coherency exitScott Williams
Separate the CPU context save and CPU coherency exit into separate functions. Change-Id: I7c5376677e293342b02b5bebdef6be2610522936 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d
2012-03-22ARM: tegra3: power: Add LP2 power mode support for CPU 0Scott Williams
Add support for forced Tegra3 LP2 low power mode on the boot processor (CPU 0) via the cluster control interface when all others are offline. Switching to the LP CPU mode is also enabled with this change. LP2 in idle and LP2 mode on the secondary processors is not yet supported. Change-Id: Icb898729f093be5e006c413f701532dd45228687 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
2012-03-22ARM: tegra: power: Align MMU shutdown code to L1 cache lineScott Williams
The MMU shutdown code must be aligned to an L1 cache line boundary. Change-Id: Ib6c976470983b7f69b45e720104fc65cae54e162 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R305325117ba1debc8d112b4c3596c158df98d75e
2012-03-22ARM: tegra: Rename flow control registersScott Williams
Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516
2012-03-22ARM: tegra: Always compile sleep.SScott Williams
Decouple LP3 (WFI) mode and CPU hotplug shutdown from CONFIG_PM_SLEEP. Change-Id: Ie959fa5e044ab4a7f84772d3b743ce2680465acc Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R8f01e646e7bf65350db44557de87c4c2a33d8059
2012-03-22ARM: tegra: Split sleep.S for Tegra2Scott Williams
Change-Id: I22bbfe62c6fed753a6852b12246f4a1f2414a96f Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R2d7985afe7ffafac651d747205e528331f5f993e
2012-03-22ARM: tegra: power: remove unnecessary barriers on LP3 idle loopScott Williams
Removed unnecessary barriers by removing the read-back of the flow controller halt register. The delay caused by the readback gets worse as the number of cores increase. By using raw writes instead, page fault handler performance improves siginificantly. In addition, the flow controller CSR interrupt and event status is cleared to ensure proper operation on Tegra3. Change-Id: I92d0a1487a16c39438038b9bfff591bc69195ab8 Reviewed-on: http://git-master/r/40461 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R98ecb17b3cdec99f69f7067ec7bdd7b00d789da9
2012-03-22ARM: tegra: power: Prefer movw/movt for loading addressesScott Williams
The movw/movt instruction pair (encapsulated by the mov32 macro) is preferred over literals for loading addresses. The use of literals for singleton data accesses can cause unnecessary cache misses and evictions for cache lines that are unlikely to be accessed again in the near future. Furthermore, certain code sequences must refrain from using data accesses. Therefore, in general, addresses should be loaded by mov32. Change-Id: I9bcc3ee191f882996197ce2edc0eb510d4ff7b4a Reviewed-on: http://git-master/r/40460 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7ddd0d9b1e2fc8ab653b9220388acbecdbf4c57f
2012-03-21ARM: tegra: sleep: flush tlbs when exiting wfiColin Cross
tegra_sleep_wfi disables coherency to prepare for possibly resetting the cpu. If an interrupt is received, it exits wfi and re-enables coherency, but it was not flushing the tlbs or the branch predictor array, which could have been updated by broadcast tlb operations that were ignored. Flush the tlbs and branch predictor array when exiting. Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191 Signed-off-by: Colin Cross <ccross@android.com> Rebase-Id: Re46c9045a33ad78789e7dee2788b470fd1071c83
2012-03-21ARM: tegra: Add suspend supportColin Cross
Tegra supports three low power modes that involve powering down the CPU. LP2 powers down both CPU cores and the GICs, but leaves the core peripherals, including the memory controller and the legacy interrupt controller, enabled. The legacy interrupt controller is used as the wakeup source, and any interrupt can wake the device. LP2 can be used in idle. LP1 is the same as LP2, but in addition turns off the memory controller and puts the DDR memory in self-refresh. Any interrupt can wake the device. LP1 could be used in idle if no peripherals are doing DMA. LP0 turns off everything in the SoC except the RTC and a power management controller, both of which run off a 32 kHz clock. The power management controller has 32 wake sources, all other interrupts can not be used to wake from LP0. These low power modes power-gate the main CPU complex, requiring a full processor state save and restore from a reset vector. Platform-specific data (power good times, PMU capabilities, etc.) must be specified when registering the suspend operations to ensure that platform power sequencing restrictions are maintained. In both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely perform this transition, the final shutdown procedure responsible for * turning off the MMU and L1 data cache * putting memory into self-refresh * setting the DDR pads to the lowest power state * and turning off PLLs is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the start of the suspend process. In LP1 mode (like LP2), the CPU is reset and executes the code specified at the EVP reset vector. Since SDRAM is in self-refresh, this code must also be located in IRAM, and it must re-enable DRAM before restoring the full context. In this implementation, it enables the CPU on PLLP, enables PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset vector to restore the rest of the system (MMU, PLLX, coresite, etc.). The LP2 reset vector is expected to be found in PMC_SCRATCH1, and is initialized during system-bootup. In LP0 mode, the core voltage domain is also shutoff. As a result, all of the volatile state in the core voltage domain (e.g., pinmux registers, clock registers, etc.) must be saved to memory so that it can be restored after the system resumes. A limited set of wakeups are available from LP0, and the correct levels for the wakeups must be programmed into the PMC wakepad configuration register prior to system shutdown. On resume, the system resets into the boot ROM, and the boot ROM restores SDRAM and other system state using values saved during kernel initialization in the PMC scratch registers. Resuming from LP0 requires the boot ROM to supply a signed recovery codeblob to the kernel; the kernel expects that the length and address of this blob is supplied with the lp0_vec= command line argument; if not present, suspend- to-LP0 will be disabled For simplicity, the outer cache is shutdown for both LP0 and LP1; it is possible to optimize the LP1 routine to bypass outer cache shutdown and restart. Includes fixes from: Scott Williams <scwilliams@nvidia.com> Aleksandr Frid <afrid@nvidia.com> Vik Kasivajhula <tkasivajhula@nvidia.com> Bharat Nihalani <Kbnihalani@nvidia.com> James Wylder <james.wylder@motorola.com> Allen Martin <amartin@nvidia.com> Change-Id: I9e4e61c2fbb8c7bb5a29b1832ea38e7ea0524c52 Original-author: Gary King <gking@nvidia.com> Signed-off-by: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Rebase-Id: R092fd9c11253416a13efb37740e961389f56dbbc
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-13 00:41:34 +0000