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path: root/arch/arm/mach-tegra/suspend.c
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2011-07-18arm: tegra: Console suspend for all boardsLaxman Dewangan
Added the board level suspend/resume and call the console suspend from board level suspend/resume. bug 820536 Change-Id: I246265241246dc0682870571c927bd23023e5aca Reviewed-on: http://git-master/r/41448 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
2011-07-15arm: tegra: suspend: Add board specific suspend/resume callsLaxman Dewangan
Adding board specific suspend and resume call apis through platform data. Added call of these function at appropriate stage of suspend/resume. Added mechanism to select the uart debug channel base address through variable so that board file can directly change this. bug 820536 bug 832273 Change-Id: Ia9ff3b8a8d2faa1071a8ff634960e6a6c8a43d40 Reviewed-on: http://git-master/r/34494 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-07-01ARM: tegra: dvfs: Add DVFS rails statisticAlex Frid
On Tegra3: complete account of in- and out-of-bound rails control. On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted, yet. Change-Id: I9dc9f53dff0f888abb718549326723a54ec4b962 Reviewed-on: http://git-master/r/37552 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-06-24ARM: tegra: sysfs write permission for user onlySachin Nikam
Giving read-write permission for user only for sysfs attributes. Group and other will have only read permission. - tegra_mc_stats: enable and quantum - susend: mode - clock: rate, parent, state File System Permission CTS expects this to pass. Bug 840409 Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/36867 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-06-24arm: tegra: power: fix LP2 scheduling in atomicXin Xie
disable_irq() will do schedule() if threaded IRQ handler is running. But suspend_cpu_complex() is called from IRQ disabled. disable_irq_nosync() should be used here because it will not sleep. BUG 841808 Change-Id: Id6cfd8c1ad305281422da878ae77b93b58f3b306 Reviewed-on: http://git-master/r/37505 Reviewed-by: Xin Xie <xxie@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-06-15ARM: tegra: pm: save/restore ahb bus registersJay Cheng
Bug 814896, 820602 Reviewed-on: http://git-master/r/35948 (cherry picked from commit 4b9158b73bd5b5ae9b1059d31e062362d4732064) Change-Id: I56c9f51bc1d6cbf455795a65d702e62ea5be1522 Reviewed-on: http://git-master/r/36676 Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-06-14arm: tegra: power: fix lp0 resume failureLuke Huang
Do not check PLLX lock bit on PLLX sanity check, since it might not be in the lock state yet. Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3 Reviewed-on: http://git-master/r/35261 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-06-03arm: tegra: disable lp0 on tegra3 A01 if it is enabledLuke Huang
Always change to LP1 even if the default is set to LP0 for Tegra3 A01 since LP0 cannot be supported for this chip revision. Bug 789450 782781 Change-Id: I2d62cf458050fcdcdded1fc5bfc08fdb2d09844c Reviewed-on: http://git-master/r/32852 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-05-31arm: tegra: Clean up SOC conditionalsScott Williams
Change SOC conditionals to make them more forward-looking. Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9 Reviewed-on: http://git-master/r/32706 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-05-23ARM: tegra: power: Fix warnings when CONFIG_PM is disabledScott Williams
Change-Id: I9d4b8c218cdfe6a91424b808f70c1ec056015783 Reviewed-on: http://git-master/r/32463 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com>
2011-05-23ARM: tegra: power: Overlap Tegra3 cpu off delayAlex Frid
Overlap cpu off delay during G-to-LP mode switch with LP mode residency. Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99 Reviewed-on: http://git-master/r/31641 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-05-18ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleepAlex Frid
Change-Id: If23b48fb414332f5dd25307a098569a5474283c6 Reviewed-on: http://git-master/r/31471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-05-18arm: tegra: power: Fix build break when CONFIG_PM disabledScott Williams
The code to select LP0/LP1 low-power mode via a sysfs node does not compile if CONFIG_PM is disabled. This fixes that error. Change-Id: If166759bd89f03335bca529cbe50a32420f802f6 Reviewed-on: http://git-master/r/31903 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-05-17ARM: tegra: power LP0/LP1 selection via sysfsKaran Jhavar
Select LP0/LP1 on runtime using sysfs node /sys/power/suspend/type. Valid selctions/commands are: 1. lp0 2. lp1 3. lp2 Change-Id: I335a8845dbfed7539ae4bf8aee3ba3b97ecb3db3 Reviewed-on: http://git-master/r/30081 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2011-04-26ARM: tegra: power: Set minimum LP2 target residencyAlex Frid
Added board level tuning parameter to specify minimum LP2 residency time (previous policy allows down to zero residency targets limited only by LP2 exit latency). Original-Change-Id: I4ae7d458fba78f35a40f138cf9489bf938715b22 Reviewed-on: http://git-master/r/28162 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Change-Id: I38e798ca6d242d136ea2353d90cc961de14f25b6
2011-04-26ARM: tegra: Use proper type for physical addressesScott Williams
Original-Change-Id: I158d2be97c795313e7e74ce9fb4ec0bdc7d95496 Reviewed-on: http://git-master/r/27559 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I0ff198daa548ed2837f7fb1794013bf0adf7e5a1
2011-04-26arm: tegra: power: Fix CPU-side LP0 entry/exitLuke Huang
1. Save/restore cpu reset handler settings on LP0 suspend/resume so that CPU state won't be destroy after LP0 resume. 2. Update bit31 in scratch4 with which CPU to wake up on LP0 resume Original-Change-Id: I4385e818ce5ca6831a42661956b6190da6c6da32 Reviewed-on: http://git-master/r/26930 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Change-Id: I4293dcb30633517d766405952b328f23d50f3f31
2011-04-26ARM: tegra: power: Re-initialize Tegra3 EMC after LP0Alex Frid
Since EMC frequency is not restored after exit from LP0, re-initialize EMC clock with the new warm boot configuration, and make sure that the 1st after LP0 clock change does not use stale timing cache. Skip Tegra2 specific EMC restoration on Tegra3 platforms. Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2 Reviewed-on: http://git-master/r/26807 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406
2011-04-26ARM: tegra: power: add partition power check before suspendJin Qian
Original-Change-Id: Ie4b29d1119bc2f640891525ab781c8de1bf64ddf Reviewed-on: http://git-master/r/23215 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Idc616485ecdb9e7c39728409d91a511e1de79e05
2011-04-26ARM: tegra: set preset_lpj to reduce time bootup secondary cpusJin Qian
Original-Change-Id: I21bf0464275dfd218084a6858bf2fb09f1eec6b6 Reviewed-on: http://git-master/r/24237 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Iad6176a44f78e68578b606b77aeb9a0624248913
2011-04-26ARM: tegra: remove reset handler from pgtableJin Qian
Original-Change-Id: I24c4016d14f90879257750ffbdf96000fd288dfe Reviewed-on: http://git-master/r/23249 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Ifd819743508b0d95fbd676092cee905ccf665136
2011-04-26arm: tegra: Enable MC early ACK and scoreboardScott Williams
Bug 791803 Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432 Reviewed-on: http://git-master/r/23584 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2
2011-04-26ARM: tegra: power: Don't enable stats interrupt on Tegra3Alex Frid
Tegra3 does not use stats monitor - do not blindly enable it on exit from LP2 Original-Change-Id: I9fbcfcefc67510f6145a78edfc35362f9c059cf9 Reviewed-on: http://git-master/r/23731 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Ib4797f3ab7ec047975edbaeac7c813e48b93ec0a
2011-04-26arm: tegra: move cpu_reset handler to iramJin Qian
reserve first 1K from iram and copy cpu_reset_handler to this location Bug 786290 Original-Change-Id: I8baaaba7bcc30e4cad2e15a368d4fcbc8e44ce07 Reviewed-on: http://git-master/r/22295 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Change-Id: I9c8010bb1d45df65ecc13d89d5168b68ed43c238
2011-04-26ARM: tegra: set lp0/1 resume entry to iramJin Qian
Original-Change-Id: Iac01de340ba79ce8038c89f3e6d166b3d48f078a Reviewed-on: http://git-master/r/21294 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Change-Id: I872ecbb8faaacad412a7d1474ddb1d469cddb8e9
2011-04-26ARM: tegra: Do not propagate legacy IRQs on LPx entryAlex Frid
Tegra3 enters LPx states via combination of core WFI and flow controller power gating mechanism. If any interrupt is pending, or fired while LPx entry procedure is executed CPU would fall through WFI, but flow controller may still initiate power down sequence. This is dangerous as CPU would be taken down while executing code. To eliminate this scenario, do not propagate legacy IRQs to CPU core on entry to LPx. Since GIC-to-CPU interrupt path is disabled in the distributer, WFI is always entered, and flow controller properly shut down CPU. The wake path: legacy IRQ-to-flow controller is kept enabled, and provide LPx exit mechanism. Bug 791458 Bug 791093 Original-Change-Id: I4f34e68335500f096790197c61f1acf83a7fc424 Reviewed-on: http://git-master/r/19971 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Change-Id: I293d5e7569b154f46945e8ea4097e3c5387a504d
2011-04-26arm: tegra: Fix compiler errors for non-SMP configurationsScott Williams
Original-Change-Id: I7bbf5e25aa041900542e33cc5904ddcc3a945aab Reviewed-on: http://git-master/r/19323 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: Ie18283ad5184b4c820c3a23b1ec8e970ad61467a
2011-04-26arm: tegra: Redesign Tegra CPU reset handlingScott Williams
- Add a single unified handler for all CPU resets. - Don't write boot confirmation notification to the reset vector. - Write the EVP CPU reset vector only once per cold/warm boot session. - Don't allow Tegra3 LP2 until all CPUs have booted. - Don't restart online secondary CPUs that are also in LP2 state when restarting CPU0 for Tegra3. - Prevent the compiler from rearranging order-sensitive register writes in boot_secondary(). - Fix incorrect return status in tegra_powergate_is_powered(). - In LP2 entry code, if a WFI request fails, retry a limited number of times. - Eliminate duplicate macro definitions. - Improve commentary in assembly functions. Bug 786290 Bug 790458 Original-Change-Id: I7582112938aa80303d1b8b1d1948d278ca662043 Reviewed-on: http://git-master/r/18091 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I56a686e2e9fc00e61e97eec4fbf5a49944ffa77c
2011-04-26ARM: tegra: Shorten cluster switch timing reportsAlex Frid
Original-Change-Id: I9e0744eb937223062e0582900fd0fb33a3ae1707 Reviewed-on: http://git-master/r/18468 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I40995652cb88c643b2e8ce5e7af707bbe7d9bfed
2011-04-26arm: tegra: Instrument cluster switch transitionsScott Williams
Original-Change-Id: I1526de69a1224f42ce3ff11ba1b6fa949c2f13a5 Reviewed-on: http://git-master/r/17787 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I43caec7348d970dc076f27cc2bb4b6ded234a38c
2011-04-26arm: tegra: Enable Tegra3 cluster controlScott Williams
Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3 Reviewed-on: http://git-master/r/15269 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae
2011-04-26arm: tegra: Decouple CONFIG_PM and CONFIG_CPU_IDLEScott Williams
Allow CONFIG_PM and CONFIG_CPU_IDLE to be set independently of each other. Original-Change-Id: I06a095a5c89fd98816bc237a790cd279f0792b2e Reviewed-on: http://git-master/r/15365 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I8bb7863dfb431bf16642f7b266e1249b6035bad4
2011-04-26arm: tegra3: Add CPU idle supportScott Williams
Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063 Reviewed-on: http://git-master/r/14167 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6
2011-04-26ARM: tegra3: Add Aruba2 power initializationScott Williams
Original-Change-Id: I44551e6e789d0eb010a0e1602cb64bf94c3277b1 Reviewed-on: http://git-master/r/14166 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I9e363a28e4af089b655ee03c03f8381bf54e75bf
2011-04-26[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
2011-04-25ARM: tegra: whistler: Power down/up core railtegra-11.2.5Prashant Gaikwad
program pwren signal of max8907c regulator to power down/up core rail on deep sleep enter/exit deep sleep mode. core_timer and core_off_timer changed as per K32. separate_req set to false as whistler pmu has combined power requests. Bug 817378 Change-Id: Ia95a61360079f919a039572cf8fd4597db9efd50 Reviewed-on: http://git-master/r/28435 Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-04-14Trusted Foundations kernel changes and driverDan Willemsen
Change-Id: I318afbe66efa346b71e82413ac6442672cef4d36 Reviewed-on: http://git-master/r/21196 Reviewed-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com> Tested-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com> Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
2011-03-03[arm/tegra] Check null pointer in suspend.cTom Cherry
In tegra_suspend_enter, we need to check mask() and unmask() for null before calling them, since there is no guarantee irq chips other than tegra will implement these functions. Change-Id: Ia6cb2c234983722bbe1202ec84eaceaf22a13450 Reviewed-on: http://git-master/r/20099 Tested-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-12-02ARM: tegra: suspend: Fix build with CONFIG_CACHE_L2X0=nAndrei Warkentin
Change-Id: I85c3a98d0c9f61153969649bb9de20a9158e9ee4 Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
2010-11-30ARM: tegra: enable emc clock updates after lp0James Wylder
Write a dummy value to EMC_MRW_0 to allow clock frequency changes after lp0. Change-Id: I2218967eaf9698eef6dcfe2e3edd89fbce2ebf1a Signed-off-by: James Wylder <james.wylder@motorola.com>
2010-11-24ARM: tegra: suspend: protect suspend functions with CONFIG_PMAllen Martin
Protect suspend/resume functions behind #ifdef CONFIG_PM. This prevents a compile error with CONFIG_PM turned off. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
2010-11-05ARM: tegra: Don't include idle time in irqsoff/preemptoff tracersTodd Poynor
Surprise bonus change: Rename tegra_enter_idle to more accurately reflect what it does. Change-Id: I1237e1271df693c109b9db8b47421f8a4c3043c3 Signed-off-by: Todd Poynor <toddpoynor@google.com>
2010-11-03ARM: tegra: suspend: use clk_get_rate_all_lockedColin Cross
Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I2d4bfd8728998903f9cff4a0f1ab41e76bdc02d7
2010-10-28ARM: tegra: suspend: Remove log spamColin Cross
Change-Id: I6ad42216d74254351f050d2a895681e5f87f269e Signed-off-by: Colin Cross <ccross@android.com>
2010-10-28ARM: tegra: suspend: Disable FIQs in suspendColin Cross
Change-Id: I9aaba8c0cada6efcdcc0fe8633f643ec5609b198 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-27[ARM] tegra: Setup regulators for suspendGreg Meiste
The regulator framework may need to change certain regulators when entering suspend. Change-Id: I584e92b3c32cbd1a63325831822e2704a3dd2774 Signed-off-by: Greg Meiste <w30289@motorola.com>
2010-10-26ARM: tegra: suspend: Save and restore PLLP in low-level suspendColin Cross
Save and restore the PLLP registers in the platform suspend code, as the CPU clock may be sourced from the PLLP registers later, before the clock resume that used to re-enable PLLP has been called. Change-Id: I0ffc18d8a7f2d62c544328bd44ca7cf62848bc44 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-25ARM: tegra: suspend: Track the amount of time spent in suspendColin Cross
Change-Id: Iee5ec7da45d3405846d8655104d9736eccedb713 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-25ARM: tegra: suspend: Fix compile issues with CONFIG_SMP=nColin Cross
Move suspend pagetable creation to suspend.c Always compile headsmp-t2.S, it's needed for LP2 resume Change-Id: I9e23c6bf72fff3e98e0549edf1f85bec823a3a38 Signed-off-by: Colin Cross <ccross@android.com>
2010-10-20[ARM] tegra: suspend: Save protected aperture across LP0Colin Cross
Change-Id: Iab66c566957cfbac8ddab615ec92e57c2164ab68 Signed-off-by: Colin Cross <ccross@android.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-20 16:18:29 +0000