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Bug 862502
Change-Id: Id119be010eadeaaebeea9a3c78313500f8dc481b
Reviewed-on: http://git-master/r/47583
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R80a63d66336349a3c05da17e4565902390763e74
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Consolidate all of the power management control flags in one
header and adjust the values of the software flags so that they
do not conflict with the values of the hardware flags.
Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4
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Rebase-Id: R03f1fc69f4859a0dc66fbd145eb0df31650de3ac
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For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration
parameter to use on Tegra for power management, and not CONFIG_PM.
CONFIG_PM does not have the required dependency on CONFIG_SUSPEND
necessary to pull in the CPU suspend/resume functionality used by
Tegra.
Also fixes compilation errors when CONFIG_PM and by implication
CONFIG_PM_SLEEP are not configured.
Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad
Reviewed-on: http://git-master/r/40458
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
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Added second level virtualization (on top of virtual cpu rate control)
to support different Tegra3 CPU power modes: low power (LP) mode and
geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is
defined as a child with two parents: virtual cpu_lp and virtual cpu_g
clocks for the respective modes. Mode switch sequence was integrated
into cpu_cmplx set parent implementation. (Before this commit mode
switch was triggered outside the clock framework, which created cpu
clock/mode synchronization problems).
Each mode clock is derived from its own super clock mux (cclk_lp and
cclk_g) to statically match Tegra3 h/w layout. (Before this commit the
code had to dynamically synchronize CPU mode and active mux selection).
This change also allowed to support PLLX output divider for low power
mode as fixed 1:2 divider with bypass control embedded into cclk_lp
parent section.
Updated auto and sysfs CPU mode switch calls to use new clock framework,
and removed clock manipulation from the low level mode switch
implementation.
Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b
Reviewed-on: http://git-master/r/24734
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be
Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
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Forbid cluster switch to G cluster if the G cluster doesn't exist.
Bug 791057
Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23
Reviewed-on: http://git-master/r/19302
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9
Rebase-Id: Re39a0fedb7bb0e2518cfd56d46c6565d4a6c2ef4
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Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.
When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.
When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.
The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.
Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827
Rebase-Id: R9cf5f5f8868c659db526cb49ddf276a79d93ef1a
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Allow run-time control of cluster switch debug messages
so they can be enabled for debuggability and disabled for
performance measurement.
Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71
Reviewed-on: http://git-master/r/17927
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379
Rebase-Id: Rb7054dcdd910d9f1b82edb485856e868a47c5034
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Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3
Reviewed-on: http://git-master/r/15269
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae
Rebase-Id: R880097280de4f9691f689ab8ab25f08020e98e23
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Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
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