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path: root/arch/arm/mach-tegra/tegra2_clocks.c
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2012-11-12Merge branch 'l4t/l4t-r16-r2' into colibriMarcel Ziswiler
Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
2012-10-18tegra: fix PWM clockMarcel Ziswiler
Fix PWM clock's special registry layout for parent clock.
2012-09-10Merge branch 'l4t/l4t-r16' into colibriMarcel Ziswiler
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
2012-08-29i2c: tegra: rename fast clock and div clockLaxman Dewangan
Rename fast clock to "fast-clk" and div clock to "div-clk" in driver and clock table to have aligned with mainline as: This is based on change: --------- commit f16e6e77a105ec53496f0d8343895da342917873 Author: Laxman Dewangan <ldewangan@nvidia.com> i2c: tegra: pass proper name for getting clock --------- Change-Id: Ie9a1972a18e2e60ac7c84c4509860cf72405ef16 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128150
2012-07-18tegra: fix tegra_emc_to_cpu_ratio() if cpu runs > 1 GHzMarcel Ziswiler
Function erroneously checked the > 1 GHz case assuming cpu frequency being in Hz rather than kHz.
2012-06-08Initial Toradex Colibri T20 L4T R15 support.Marcel Ziswiler
2012-05-30arm: tegra: resolve compilation time warningsSanjay Singh Rawat
Warnings removed are related to unused variables/labels, structure/argument type mismatch, copyright update, function return type mismatch and wrong C coding style. Bug 949219 Change-Id: Ib748d12d5ab3cfc35118be28c29983081cca6cbb Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/103770 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-05-25ARM: tegra: clock: Update secondary pll dividers resumePrashant Gaikwad
During resume from LP0 on Tegra2 always enable pll secondary dividers before clocks restoration (to make sure clock sources are enabled). Restore actual secondary dividers settings after clocks are restored. Bug 965928 Bug 953030 Change-Id: Id0cd99b601f90ad9fe8452817810969e41002199 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed on http://git-master/r/#change,104661 (cherry picked from commit 6350d1fd475373779cf5110403717b2c84e723ba) Change-Id: Ic50477603b97a99d2ac2c926df1728faa107b108 Reviewed-on: http://git-master/r/104668 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-24ARM: tegra2: clock: Put Tegra2 clocks to known statesJong Kim
Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and video clocks into known state, so that L4T Ventana/Harmony works on u-boot. bug 967065 Change-Id: If7637b13e0daf1823fa0fe694a87870f4601e4df Signed-off-by: Jong Kim <jongk@nvidia.com> (cherry picked from commit df259e5b4e0692733e4ae362ea19de01d4b9a72f) Reviewed-on: http://git-master/r/104606 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com>
2012-05-06arm: tegra: update the udc driver nameRakesh Bodla
Update the clocks structure to use new udc driver name. Also, update the device structure. Bug 887361 Change-Id: I0fd846ab177e8651f285bcb9796361d30967b830 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/99448 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-03ARM: tegra2: clock: Put Tegra2 clocks to known statesJong Kim
Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and video clocks into known state, so that L4T Ventana/Harmony works on u-boot. bug 967065 Change-Id: If7637b13e0daf1823fa0fe694a87870f4601e4df Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/95734 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-03ARM: tegra: clock: Add DSI implicit dependency on PLLPAlex Frid
Added dsi fixed clock entry derived from PLLP_OUT3. This would allow DC driver to properly ref-count implicit dependency of DSI operations on PLLP_OUT3 clock. Bug 933653 Change-Id: I71e6ada13f9d231c5a4924f345cdbf7cf05cd59e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/98103 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-23ARM: tegra2: clock: Dynamic rate configurationShashank Sharma
support dynamic clock rate configuration for pll_d. Till now tegra2 used to look into a pll_d frequency table to match input and output frequencies, resulting fixed pll_d output frequencies. Whereas tegra3 had code to configure pll_d for any desired rate using dynamically generated m,n,p values. Bug: 931908 Change-Id: I15322e2e4ac0aba58502575cdc83ca4a4542d1e4 Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/90361 Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-15ARM: tegra: clock: Entry for spi-sclk clock controlLaxman Dewangan
Tegra's spi requires some minimum sclk clock frequency for proper functioning. Making entry for spi-sclk clock so that spi driver can get the proper clock for controlling the minimum rate of sclk. bug 949393 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/89524 (cherry picked from commit 542cbe457b1b19b8fdf8cbf193e38a00027060c2) Change-Id: I3f829b36b1b42bb8b1c6e4e21745855e113c17c1 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/90294 Reviewed-by: Automatic_Commit_Validation_User
2012-02-21ARM: tegra: clock: Support for clock source control without enable bitLaxman Dewangan
Some of controller like i2c requires a different clock source which is not enabled/disabled by the clock bit in CAR register set. Handling such cases by looking for PERIPH_NO_ENB flag when calling clock enable/disable functions. Change-Id: Id0d1df7946d1c83d769116ae7a91546bd59d4478 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/84709 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-21ARM: tegra: clock: Add i2c fast clock entryLaxman Dewangan
Adding i2c fast clock entry which is derived from pllp_out3. This is non-muxed input clock for i2c and does not have any enable bit on CAR register set to enable/disable through clock-reset registers. bug 933653 Change-Id: I0c50d6570b88510e3acef2ed0993e4305b2e34e8 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/84693 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-15ARM: tegra: clocks: Consolidate input frequency measurementsScott Williams
Consolidate the functions used to measure the input frequency into a single implementation and perform the measurement only once. Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-15ARM: tegra: clocks: register emc clock for camera on tegra2shivabassu boragalli
Register emc clock for camera on tegra2. Bug 930239 Signed-off-by: Shivabassu Boragalli <sboragalli@nvidia.com> Reviewed-on: http://git-master/r/83043 (cherry picked from commit 06664f4c595b6e91dfa5e5d7ffc3761d328e31c9) Change-Id: I576e7e874d31dd4bb36752e119531aa107cb5112 Reviewed-on: http://git-master/r/83396 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-14Revert "ARM: tegra: clock: Add i2c fast clock entry in shared clock"Simone Willett
This reverts commit 0fbe4ffbcd3fcff93cc574d2bbea94e9971c79cf Change-Id: Iea7bdd09565d5de8e004db2b8e5e3fbb3b958531 Reviewed-on: http://git-master/r/83847 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-14ARM: tegra: clock: Add i2c fast clock entry in shared clockLaxman Dewangan
Adding i2c fast clock entry which is derived from pllp_out3. bug 933653 Change-Id: I5c799edecec7ee7060ff2a11cf1cb22a1c702e26 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/78995 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-01-16ARM: Tegra2: clock: Update TWD rate with CPU ratePrashant Gaikwad
When CPU is clocked from backup PLL, TWD rate was not updated. Change-Id: I3ee1e210607393bfd06227adac46141b752768dc Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/74003 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-on: http://git-master/r/75149 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-01-06arm: tegra2: clocks: add fuse and fuse_burn clocksVarun Wadekar
These clocks are needed for fuse programming and was added to the tegra3 code but not to the tegra2 code. Bug 906200 Change-Id: I3ff13e526c252406a5107c5e9f7dd0af8f31c98b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/72136 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-06ARM: tegra: cpufreq: add cpu to emc mapping for AP25Prashant Gaikwad
With current mapping for CPU frequency greater than 816 MHz EMC frequency will be always 600 MHz. AP25 max EMC frequency is 760MHz. If CPU frequency is greater than 1GHz then set EMC frequency to 760 MHz. Change-Id: I617e1637bd14c3c8560ffdfa17769f6554059609 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/67893 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-12-21ARM: Tegra: Rename clk_dev2 to cdev2Victor Ryabukhin
Originaly renaming was done in commit ddb7d5d80 However, some of clock names ramained unchanged. Fixed this. Bug 917441 Change-Id: I0bac986c0be6e66fc4ae258563091d4c7d9c45c3 Signed-off-by: Victor Ryabukhin <vryabukhin@nvidia.com> Reviewed-on: http://git-master/r/70973 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2011-12-08ARM: tegra: clock: Add clock support for tegra2 dsiAnimesh Kishore
Added clock entry for dsi in the list. Bug 895937 Change-Id: I1d3a82d5ac692d7c3a0d89df89078253cda1d46d Reviewed-on: http://git-master/r/63008 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2011-11-30tegra: NOR: Allow mapping NOR aperture and clocks.Manoj Chourasia
Renamed client driver for nor clock from "nor" to "tegra-nor". Add NOR flash aperature as valid address range in ioremap. Reviewed-on: http://git-master/r/44746 (cherry picked from commit 151b678580c43fa53bacd22f7f3d847d3eac3f6d) Change-Id: I61bcb316f3e9f757f24260bc24e2c4378f8e3326 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/66706 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R2e2a9a1ee7162a8073758150e56d5c1f8aa1f2fd
2011-11-30ARM: tegra: clock: Enable EMC scaling for AP25Prashant Gaikwad
Workaround added to enable EMC scaling for AP25. PLL switching support added for 300MHz EMC scaling step. Bug 892505 Reviewed-on: http://git-master/r/#change,41718 Reviewed-on: http://git-master/r/#change,41720 Reviewed-on: http://git-master/r/#change,60861 Change-Id: I885b8dc4e3b6124ebed572c06cea773de6c83471 Reviewed-on: http://git-master/r/64465 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: Rb8e58cfa7fe1106978030c8aea292e95a7a5da2b
2011-11-30ARM: tegra: clock: remove warningsPrashant Gaikwad
Removed unused variable warnings. Change-Id: I6307773d069fe350604cfa2a7cb28664c081b5b6 Reviewed-on: http://git-master/r/64456 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R9367a80be4cef31b14b9837d52123d76ffb7d982
2011-11-30ARM: tegra2: clock: Increase max_rate of uart clocksPradeep Goudagunta
Increase max_rate of uart(a,b,c,d,e) clocks to 800MHz based on board SKU. Bug 898245 Change-Id: I1a3fd52f3397b73225e43813b76edf38451d79e9 Reviewed-on: http://git-master/r/62985 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rfbc816b0e8775fd5aa72fc4ee623edea35d72d3d
2011-11-30ARM: tegra2: clock: Update bus operationsPreetham Chandru
Relaxed bus set rate success condition: instead of checking for the exact rate check for the closest rate. This makes bus clocks configurable from sources/PLLs with variable frequencies. Bug: 869054 Signed-off-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-on: http://git-master/r/50747 (cherry picked from commit 61313ed2494424513cb6e42c22cb7ca31f21473e) Change-Id: Id4c9ff63da4cefb1d13888a627f0757a3b941994 Reviewed-on: http://git-master/r/56659 Tested-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Mursalin Akon <makon@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com> Rebase-Id: R57ac9f6cebe9df5e02dadac345653e2f3cf23e83
2011-11-30ARM: tegra: clock: Re-factor shared bus lockingAlex Frid
Current code: - on tegra2 unnecessary covers with bus lock shared user state update - on tegra3 does not cover shared bus rate update at all Modified to cover with bus lock shared bus rate update only on both tegra2 and tegra3. Change-Id: Iaa2597136a521adf4285c61eb579c917c2c7965c Reviewed-on: http://git-master/r/55640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R1b28f32ae37d47c56855023b18c943bf8fd93c74
2011-11-30arch: arm: tegra: Add SPDIF driver supportSumit Bhattacharya
Bug 872652 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Change-Id: I7b948b820434721511c008f644b69d93c23865e1 Reviewed-on: http://git-master/r/53094 Tested-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R3fb55fe060065d76fb18010ad249e6ee0f96a944
2011-11-30nvhost: power: Separate module shared clocksTerje Bergstrom
Register clocks that are shared amongst modules (emc, epp) as separate clocks. This way setting EMC clock for 2D does not interfere with EMC clock needs for 3D or MPE. Bug 868554 Original-Change-Id: I5c7dddc8f1d67969865918e577bd24b274d9e897 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/49603 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R6d25c0765bbaf73f50568b7438c3b4376befef9b
2011-11-30ARM: tegra: clock: tegra2_pll_clk_set_rate() process p field is greater then 2.Bo Kim
This change makes tegra2_pll_clk_set_rate() will process for p field is greater then 2. It helps to increase VCO. Bug 852217 Bug 842032 Reviewed-on: http://git-master/r/47492 (cherry picked from commit e1fefd8a7fb9751ddfad95e469666f3c876123a8) Original-Change-Id: Id49b33cd8e568c6e5b619988a148242a85867eca Reviewed-on: http://git-master/r/49585 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bo Kim <bok@nvidia.com> Tested-by: Bo Kim <bok@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R0b4910e4265303f70b7c449d79c9c3ea8a67aa6d
2011-11-30ARM: tegra: add 504MHz entries to pll_d tableJoseph Lehrer
bug 837571 (cherry picked from commit bf2187ca9ebd53a4fdc33135cf2e491361c51f15) Original-Change-Id: Ie961c871f25706deb415dd7820aa1cb0bec79c4b Reviewed-on: http://git-master/r/40379 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R065f0cba23ebe1b6be2a8595d4e71e90ae0e14f2
2011-11-30ARM: tegra: clocks: Add shared sclk for statmonPrashant Gaikwad
H/W statistics monitor for AVP controls sclk depending on load. Instead of overriding avp.sclk rate, separate sclk client added for statmon so that busy hints from AVP can be handled. Bug 831892 Reviewed-on: http://git-master/r/36057 (cherry picked from commit a19f85a8a7af722bcfd729297e682574dc22de7b) Original-Change-Id: I216ef8eac46ac0bfdd8d439b197f14af37720db3 Reviewed-on: http://git-master/r/39795 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rbbc91472cf6dbadbe773fc72a9f1af4f96bd5af9
2011-11-30tegra: clocks: Remove shared clocks from sku_limitsmchourasia
"avp.sclk" and "bsea.sclk" are shared clocks and should be removed from sku_limits table as shared clocks are registered later and not available at the time of putting rate limits. Original-Change-Id: Idc85d37a06e764e03f08e31582dbd16c77ae4b16 Reviewed-on: http://git-master/r/38271 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R6c4d95bbf32d713a3e78201f49bc612423e8b35c
2011-11-30ARM: tegra: add support for hardware statistic counterPrashant Gaikwad
Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS modules. This commit adds the support for AVP statistics gathering and controlling avp clock during video playback. Bug 831892 Reviewed-on: http://git-master/r/35647 (cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e) Original-Change-Id: I441acbaf2cb8dd776529bafd4e13f50e31849afa Reviewed-on: http://git-master/r/39657 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7271973f142f14fc8a11bdbc33ae6f76f6fd38b0
2011-11-30ARM: tegra: clock: Use bus lock to protect shared bus updateAlex Frid
Protected shared bus update with bus lock - common for all shared bus users (update procedure was already covered by individual shared users locks, but it did not prevent concurrent access to shared rates list). Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507 Reviewed-on: http://git-master/r/39918 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f
2011-11-30ARM: tegra: Fix mutex in atomic context when updating TWD freqScott Williams
The CPU frequency change notifer runs in an atomic context but obtaining the current CPU frequency requires taking a mutex because updating the CPU frequency involves the regulator. Instead of directly parenting the TWD clock on the CPU clock, make the TWD a "detached child" of the CPU clock whose rate is updated whenever the CPU frequency changes. Change-Id: I49e15f85f269fb3ed0bcaee36ff739b4f064d6b8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7aa10f2576752390464586bc629c972802beb989
2011-11-30ASoC: Tegra: Complete Tegra->Tegra20 renamingStephen Warren
Rename Tegra20-specific Kconfig variables, module filenames, all internal symbol names, clocks, and platform devices, to reflect the fact the DAS and I2S drivers are for a specific HW version. Signed-off-by: Stephen Warren <swarren@nvidia.com> Rebase-Id: Rb2430e3fc84547430d6727fbd6adbf64afd00184
2011-11-30UPSTREAM: ARM: Tegra: Rename I2S clocks to match driver nameStephen Warren
The driver is tegra-i2s not just i2s. Rename the clocks to match, so that clk_get_sys can look up by driver name. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I939aef5390ca7884a178d329ee6e6663492b885e Rebase-Id: R0dcc423f24d2bc204c3a60b7b57dc8580a9c91b7
2011-11-30ARM: tegra: power: Use CONFIG_PM_SLEEP instead of CONFIG_PMScott Williams
For Linux 2.6.39, CONFIG_PM_SLEEP is the proper kernel configuration parameter to use on Tegra for power management, and not CONFIG_PM. CONFIG_PM does not have the required dependency on CONFIG_SUSPEND necessary to pull in the CPU suspend/resume functionality used by Tegra. Also fixes compilation errors when CONFIG_PM and by implication CONFIG_PM_SLEEP are not configured. Change-Id: I8bb380ae7c6b22759bfbc223febc28f585111aad Reviewed-on: http://git-master/r/40458 Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R61d656cd67439aa9f466c381845d7a4685fc8648
2011-11-30arm: tegra: clock: update conid for uartPradeep Goudagunta
changing clk con id to uarta,uartb and etc., has broken tegra hsuart clk_get functionality so changing it back to NULL. Bug 837140 Original-Change-Id: I8f01e86b76559505b85db0e520100de10a54e761 Reviewed-on: http://git-master/r/35676 Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com> Tested-by: Rajkumar Jayaraman <rjayaraman@nvidia.com> Rebase-Id: R4edc205bcba93cc86788f8f3cdb1af883d562569
2011-11-30arm: tegra: clock: Adding clock info for 8250 driverLaxman Dewangan
Adding clock information in the clock table for the serial driver 8250. bug 832273 Original-Change-Id: I45acf988d2cf79d28cf9467d89fbfab49141803e Reviewed-on: http://git-master/r/35050 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Rc396fb7e5545b276a15548d72bb4a0cbfb24942f
2011-11-30arm: tegra: clock: Reading APB bus before disabling clockLaxman Dewangan
It may be possible that write operation on apb bus does not get complete before disabling clock if the clock is disabled just after the write on apb bus. To have proper sequence of operation, it is require to read back the apb bus to make sure the write operation is completed. bug 830481 Original-Change-Id: I7f9f68f4cd6d39cf0bd697ddd236c4ce733dcf43 Reviewed-on: http://git-master/r/34413 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R204c12464faad2d3e36fbd1b583e798fab99e248
2011-11-30ARM: tegra: clocks: sku limit for pclkPrashant Gaikwad
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk. pclk max rate changed to 150MHz for AP25. Bug 821534 Reviewed-on: http://git-master/r/31311 (cherry picked from commit 3655e9a4940bfa39ba103903f2e2f1d5f0cf7e2d) Original-Change-Id: Id10c322892e646c2c1f74cbf36268608fc268493 Reviewed-on: http://git-master/r/32874 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R7b21164fa84f78febf445ce4b60e92b1d70c6406
2011-11-30Revert "arm: tegra: clock: Reading APB bus before disabling clock"Niket Sirsi
This reverts commit 9b2aa51a8b4913948e3061706498c7f91d5aa827. Original-Change-Id: Ie197a9822329c7e36735ef673d0baf69923197de Reviewed-on: http://git-master/r/34389 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R82febd144c3064240a199a67a906b8b481ccd2f1
2011-11-30arm: tegra: clock: Reading APB bus before disabling clockLaxman Dewangan
It may be possible that write operation on apb bus does not get complete before disabling clock if the clock is disabled just after the write on apb bus. To have proper sequence of operation, it is require to read back the apb bus to make sure the write operation is completed. bug 830481 Original-Change-Id: If4767b77a9ac8fdf3253e19d6aebed6c1d13dc5a Reviewed-on: http://git-master/r/32556 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R16af6944cdb3cb87ef6c62fe90dd6481af2a2c2a
2011-11-30ARM: tegra: clocks: init shared clk after sku limitPrashant Gaikwad
shared clock rate is dependent on its parent max rate. Parent's max rate get updated in sku limit init depending on the sku value. Hence initialize shared clocks after sku limits are applied. Bug 821534 Original-Change-Id: I505b03bc03702c198f07f36437b2e9f3fc8e50cb Reviewed-on: http://git-master/r/29803 Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd20682be06b2edec9acdfc8fd0b6f110dfc94166
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-14 05:50:41 +0000