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path: root/arch/arm/mach-tegra/tegra2_dvfs.c
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2012-04-10arm: tegra20: pm: Reduce CPU min voltage to 0.8VPrashant Gaikwad
Bug 955718 Reviewed-on: http://git-master/r/94164 (cherry picked from commit 1be4c3a94dd95a9c0fae2317983b0d7e44e39a1f) Reviewed-on: http://git-master/r/94407 (cherry picked from commit 00799dbe21f5835b729f2fe9fcf95f30aa0b149f) Change-Id: I909a15ead2d4ecb3dc416b8d3863fa8cb3645501 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/94164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-10arm: tegra: dvfs: optimized bin0 entriesPrashant Gaikwad
Updated optimized bin0 entries for AP25 CPU dvfs. Bug 955718 Bug 643434 Reviewed-on: http://git-master/r/57303 (cherry picked from commit 6e5c759fcdfcdf4d1306fe5c9e33bf2dd5458076) Reviewed-on: http://git-master/r/94406 (cherry picked from commit 61317b2ed1a259d5c0460aec8bc1d9f4e2275922) Change-Id: I84cccfde1c0fa292c64a9acd2c96643416f00735 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/90306 Reviewed-by: Automatic_Commit_Validation_User
2012-03-13tegra2: dvfs: enable dvfs for sdmmcShridhar Rasal
Enabled dvfs table for sdmmc clocks bug 893886 Reviewed-on: http://git-master/r/82687 (cherry picked from commit 45c6c0426fdde8d338d10029cc83b598e7e49e61) Change-Id: I26e07b45ef6331b99c57dd792ad0cc66a94242fb Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/89410 Tested-by: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-12-15tegra2: dvfs:vdd_core voltage must be 120mv higher than vdd_cpuJay Cheng
bug 880495 Change-Id: Ic89487c6296b20377ee12a135d06bef5b5c8b6fa Reviewed-on: http://git-master/r/68983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30Revert "HACK: disable DVFS - tegra otg was calling clk_enable in atomic context"Gaurav Sarode
This reverts commit a97ac421395cfb5998a53ccdc07c9a5f9c6777cd. Fix bug 864254 Change-Id: I61b97e033413f7d61c06da83d9b6f971df9019cc Reviewed-on: http://git-master/r/49685 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Raf5717982cd8768f948f446bfaa48265bfd723f6
2011-11-30arm: tegra: dvfs: use 1.1 v for usbWen Yi
Set the working voltage for USB to 1.1 v. Bug 796594 Reviewed-on: http://git-master/r/30219 (cherry picked from commit af08f51a8c51b7b8d3f25ee7a2372f9d423b78e7) Original-Change-Id: I71332eaa238c1116bcb2c2555654ea65a648c702 Reviewed-on: http://git-master/r/40305 Reviewed-by: Xin Xie <xxie@nvidia.com> Tested-by: Xin Xie <xxie@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R17971c5c60e28d8816955cf6d834df4c7d3c272b
2011-11-30HACK: disable DVFS - tegra otg was calling clk_enable in atomic contextDan Willemsen
Rebase-Id: Rfab78b9c453b9c1f55c780f8c99507a58cbeaece
2011-11-30Update copyrightsScott Williams
Original-Change-Id: I2ffeaf6f8dfeb279b40ca6f69f6c9157401a746a Rebase-Id: Rd8ebde470ad475b826857413018a2da8e1fdea25
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
2011-11-30ARM: tegra: dvfs: Update MPE dvfs tableAlex Frid
Updated MPE clock dvfs table with recent characterization data. As a result MPE clock limit is increased to 300MHz across all tegra 2 SKUs. Original-Change-Id: Ibe700770c7d109a397cb140b6f217a8d48509ff1 Reviewed-on: http://git-master/r/16662 Reviewed-by: Amit Kamath <akamath@nvidia.com> Tested-by: Amit Kamath <akamath@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R6e5c6cef46a05527a31d70ed87c6d3f58077c5e7
2011-11-30ARM: tegra: dvfs: Update SCLK dvfs tableAlex Frid
Updated system bus clock dvfs table with recent characterization data. As a result nominal core voltage for SKUs with 240MHz SCLK limit increased from 1.2V to 1.225V. Original-Change-Id: I42a35f848bb0a410d393d930ddf1a87f86f25280 Reviewed-on: http://git-master/r/16272 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rda324012f2f1610da9480023d9fafc00ab9fdbd4
2011-11-30ARM: tegra: dvfs: Expand core voltage scaling tablesAlex Frid
Add per process_id DVFS tables for tegra2 clocks, that are boosted by the new tegra2 skus. Still use common worst case tables for other clocks. Updated EMC dvfs table with recent characterization data. Original-Change-Id: I883ccca54597b87f37c08bc2d7444190f80234f5 Reviewed-on: http://git-master/r/16079 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R47ff0f041def21ee650152224c6b5e654e5d1ab9
2011-11-30ARM: tegra: dvfs: Add 1.3V level to core DVFS tablesAlex Frid
Original-Change-Id: Ia651b5c5f6cc0f6811b593bc795e6b7b97eb1741 Reviewed-on: http://git-master/r/16078 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Re566c05f4e91bc1a0a2c24489edf680722c349fa
2011-11-30ARM: tegra: dvfs: Expand CPU voltage scaling tablesAlex Frid
Added CPU DVFS tables for new tegra2 revisions/skus. Implemented table selection based on chip speedo and process corner. Original-Change-Id: Ic2aa7ff2b487a37a0a97d4f40453ff033a562207 Reviewed-on: http://git-master/r/13397 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd090645567dbff203637e72fef3ead73019b4dcf
2011-11-30ARM: tegra: Add dvfsColin Cross
Change-Id: I865e52cae592507c642b92dde3a8293db2d0228f Signed-off-by: Colin Cross <ccross@android.com>
2011-02-21ARM: tegra: clock: Drop CPU dvfsColin Cross
The existing version did not extend well to core dvfs, drop it for now until the new clk api with clk_prepare and clk_unprepare is ready and non-atomic clocks are possible. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
2010-10-21[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
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