| Age | Commit message (Collapse) | Author |
|---|
|
Fix DDR2 vs. LPDDR2 EMC memory frequency scaling.
|
|
Optimization that primarily addresses when cpu frequency
is low but a high memory bandwidth is needed.
Change-Id: I4f800c2368191c744aefd9f83eb96e4c108dbcc3
Signed-off-by: James Wylder <james.wylder@motorola.com>
|
|
Update tegra_init_emc to provide generic memory
vendor matching. Read values from EMC_MRR_0, to
uniquely identify memory types and compare them
to table of memory passed in.
Change-Id: Ie116fa6f497076149c87ff6c0ae0621309bac65f
Signed-off-by: James Wylder <james.wylder@motorola.com>
|
|
The frequency memory bus on Tegra can be adjusted without
disabling accesses to memory by updating the memory
configuration registers from a per-board table, and then
changing the clock frequency. The clock controller and
memory controller have an interlock that prevents the
new memory registers from taking effect until the
clock frequency change.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>
|
