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Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94
Reviewed-on: http://git-master/r/15349
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777
Rebase-Id: R3cab0fa7760e2c6eb5d6e84bbc3dca8f6fe3d3fa
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Update tegra_init_emc to provide generic memory
vendor matching. Read values from EMC_MRR_0, to
uniquely identify memory types and compare them
to table of memory passed in.
Change-Id: Ie116fa6f497076149c87ff6c0ae0621309bac65f
Signed-off-by: James Wylder <james.wylder@motorola.com>
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The frequency memory bus on Tegra can be adjusted without
disabling accesses to memory by updating the memory
configuration registers from a per-board table, and then
changing the clock frequency. The clock controller and
memory controller have an interlock that prevents the
new memory registers from taking effect until the
clock frequency change.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Cross <ccross@android.com>
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