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path: root/arch/arm/mach-tegra/tegra3_clocks.c
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2012-01-31ARM: tegra: clock: Decrease CPU rate range low boundAlex Frid
Add 51 MHz entry to cpufreq tables (102 MHz was minimum supported rate before). Bug 922351 Reviewed-on: http://git-master/r/77511 Change-Id: I20eea30cdadfb9efbf6489f8aaf5934f653af128 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78032 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-31ARM: tegra: clock: Restrict Tegra3 PLLC usageAlex Frid
On Tegra3 PLLC should be used as a parent clock only for graphics bus (cbus) modules and secondary PLLC divider. Fail set parent API if PLLC is selected as a new parent for other clocks. Reviewed-on: http://git-master/r/77253 Change-Id: I564278dcdd62c17c6446218955c366b1612c73b3 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78030 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-31arm: tegra3: change min_rate for sclkWen Yi
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. BUG 922351 Reviewed-on: http://git-master/r/76959 Change-Id: I6a2871d1cc02a19829cf397e9583122e02255f81 Signed-off-by: Wen Yi <wyi@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78010 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-01-30ARM: tegra: clock: Update CPU clock scaling dependenciesAlex Frid
Added Tegra3 MSelect clock to memory on CPU clock dependencies: MSelect rate is scaled as half of CPU rate, up to 102MHz. Prevented CPU clock increase if updates of dependent clocks (EMC and MSelect) have failed. Reviewed-on: http://git-master/r/76485 Change-Id: I679b60eb5aa13d5cca2b9751ff2c8c2fb866a076 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77767 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30ARM: tegra: clock: Add support for Tegra3 MSelect clockAlex Frid
Added clock for memory path selection module (MSelect) to Tegra3 peripheral clocks. Initialized MSelect clock rate to 102MHz. Reviewed-on: http://git-master/r/76484 Change-Id: I73676882d8e6805445985b23257bcf6410e8c3e0 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77766 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30tegra3: fix pll_c frequency tableAlexandre Courbot
tegra_pll_c_freq_table had an error in the output clock rate. This patch fixes it so that the formula o =(i * (n / m)) holds true. Bug 917377. Reviewed-on: http://git-master/r/76943 Change-Id: I06cb132e9ac05dac905ef2ef0437f5278cf916e5 Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77734 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-30ARM: Tegra: clock: Add PERIPH_ON_APB flag to HDA clocksSumit Bhattacharya
Bug 896827 Reviewed-on: http://git-master/r/75867 Change-Id: Id37fe5557f6d7993f6df424d0a8d027acb6bd1b4 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77310 Reviewed-by: Automatic_Commit_Validation_User
2012-01-30ARM: tegra: clock: Auto-detect PLLP rate in clock initAlex Frid
Tegra3 platform may boot with one of the predefined fixed PLLP (peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This commit implements auto-detection of PLLP rate, as well as CPU, and system bus PLLP dependencies configuration during clock tree initialization. Bug 928260 Change-Id: I65ea4db2e5cfe96f13566c93e882a3be9deaa129 Reviewed-on: http://git-master/r/75850 Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/77295 Reviewed-by: Automatic_Commit_Validation_User
2012-01-24ARM: tegra: clock: Fix Tegra3 clock lockingAlex Frid
Added locking for non-atomic access to shared registers for the following clocks: - secondary PLL dividers - audio doublers - cml (sata/pcie) clock controls Added locking for peripheral clocks secondary reference counting (register access is atomic, but some clocks may share an enable bit). Updated comments for external output clocks (shared access already protected). Reviewed-on: http://git-master/r/76163 Change-Id: If656bf13d966bf4590d55c5509860110efea937b Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76814 Reviewed-by: Automatic_Commit_Validation_User
2012-01-20ARM: tegra: clock: Add Tegra3 0.95V core voltage stepAlex Frid
- Expanded Tegra3 DVFS tables with 0.95V core voltage step - Updated cbus minimum rate calculation, since cbus can not run at 0.95V - Updated PLLM dvfs initialization, since PLLM can no longer be voltage independent, even when its usage is restricted. Bug 817679 Bug 841336 Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4 Reviewed-on: http://git-master/r/74141 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76463 Reviewed-by: Automatic_Commit_Validation_User
2012-01-16ARM: tegra: clock: Skip clocks in Tegra3 CPU set rateAlex Frid
Reduced Tegra3 CPU clock frequency by skipping every other clock during clock rate change when either old or new rate is above 800MHz. This limits max possible frequency jump when switching between main and back-up clock sources. Added sysfs entry for minimum time to run at reduced frequency (in microseconds): /sys/module/tegra3_clocks/parameters/skipper_delay. Default delay is 10us. It should be adjusted by board initialization code based on board power distribution grid capabilities. Bug 868692 Change-Id: I0c32a3eb91512ba610c4f842bd22ef08e9c889d0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/72682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-on: http://git-master/r/75140 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12ARM: tegra: clock: Add Tegra3 camera EMC shared userAlex Frid
Bug 913674 Change-Id: I22ee3a56478da5e4d6f989f306d9b8d900ac3b92 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/73656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nathan Lord <nlord@nvidia.com> Tested-by: Nathan Lord <nlord@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/74554 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12ARM: tegra: clock: Split Tegra3 G/LP CPU backup ratesAlex Frid
Separated Tegra3 G and LP CPU backup rates used while main CPU PLL is re-locking. These rates are selected low enough to be safe at minimum voltage, but high enough to avoid voltage droop when CPU clock is switched between backup and main clock sources. Bug 868692 Change-Id: I6b07323a5d3a69d0834b743596aca1e5499781a4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/71132 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Reviewed-on: http://git-master/r/74551 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-01-06arm: tegra: Disable pll_p_out clocks by defaultScottPeterson
Disable unused pll_p_out clocks until they are needed to reduce power. Change-Id: I60c2a7ca50a957f23ca20ec559dbbb1aa26ca797 Reviewed-on: http://git-master/r/72464 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-01-06ARM: tegra: dvfs: Update Tegra3 CPU DVFS tablesAlex Frid
Bug 817679 Bug 841336 Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/71755 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-04tegra3: clock: Support for divisor 15.1Laxman Dewangan
Uart clock source has divisor of 16 bits where LSB is 0.5. Adding support for divisor 15.1 and configuring uart for use the 15.1 type divisor. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: Ifdd77041e7abb43026bbfb273f6e12923d64d607 Reviewed-on: http://git-master/r/70324 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2011-12-15ARM: Tegra: Add dev_id and con_id for audio_sync clocksSumit Bhattacharya
For I2s slave mode i2s clock needs to be generated from audio_sync clock. So depending on codec master/slave mode parent of i2s clock needs to be changed in runtime. To support this i2s_sync, audio and audio_2x clocks needs to be accessed from I2s driver. To facilitate accessing of all these clocks add dev_id and con_id fields for these clocks. Bug 911332 Change-Id: I92094ac563de8025f7d88eb47e439098c98111bb Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/69756 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
2011-12-15ARM: tegra: clock: Use Tegra3 PLL lock indicatorsAlex Frid
Bug 873599 Change-Id: Ice84a63d90d39105e53505282fe126e56c4749db Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/68897 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2011-12-08ARM: tegra: clock: Enforce Tegra3 cbus parent assignmentsAlex Frid
Tegra3 graphics bus (cbus) modules do not use PLLM as a clock source after boot. Explicitly enforced this policy now by failing set parent API if PLLM is selected as a target for any cbus clock. Bug 884419 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit eb2662b7d90af77ee01202e57afa3ed46d4f9053) Change-Id: Ia17972c8c711d3498541ad62aef3961656433665 Reviewed-on: http://git-master/r/67832 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: clock: Update Tegra3 cbus operationsAlex Frid
- Doubled PLLC (cbus parent) rate to make sure that cbus clients always have only even dividers. - Added new shared bus user mode - SHARED_AUTO for user (like Host1x) that just follow the bus, but by itself does not require bus rate above the minimum. Bug 895245 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit e95329c67d4efc424d3408b363e092c02c066ef7) (cherry picked from commit 773e089f2ab676e9ea8afd7aaa0458654a3772d9) Change-Id: Ie1488f38e3cb948d69738c2eef4ae9cd7ae0b47d Reviewed-on: http://git-master/r/67011 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rdd00a21fc2f58efdfeec5733c0307627da1fb430
2011-11-30tegra: NOR: Allow mapping NOR aperture and clocks.Manoj Chourasia
Renamed client driver for nor clock from "nor" to "tegra-nor". Add NOR flash aperature as valid address range in ioremap. Reviewed-on: http://git-master/r/44746 (cherry picked from commit 151b678580c43fa53bacd22f7f3d847d3eac3f6d) Change-Id: I61bcb316f3e9f757f24260bc24e2c4378f8e3326 Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/66706 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R2e2a9a1ee7162a8073758150e56d5c1f8aa1f2fd
2011-11-30ARM: tegra: clock: Support restricted PLLM usageAlex Frid
Added configuration option TEGRA_PLLM_RESTRICTED - when enabled, PLLM - memory PLL - usage may be restricted to modules with dividers capable of dividing maximum PLLM frequency at minimum voltage. When disabled, PLLM is available as a clock source with no restrictions (current configuration), which may effectively increase lower limit for core voltage if high grade SDRAM is used. Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but keep them disabled by default. Bug 884419 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61) (cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3) Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa Reviewed-on: http://git-master/r/66512 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R22de0f09e7af2640499ec8cd96e974328d78bace
2011-11-30ARM: tegra: clock: Return shared_bus_set_rate() errorsAlex Frid
Returned error code from Tegra3 shared_bus_set_rate(). (cherry picked from commit b9aea1656af4d3e17433c82611fe5e7146a41733) Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 92cd5c809536e4c7c8a30b08d033346bb4f147a3) Change-Id: Iaa1c93e2303f0d4e6dd35f00bbd7010e3ef90a3f Reviewed-on: http://git-master/r/64768 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: Rbb19019bca965394d433cf16142e8b51c80b7af0
2011-11-30ARM: tegra: clock: Add Tegra3 emergency throttlingAlex Frid
Add Tegra3 emergency throttling API to directly control G-CPU super clock skipper underneath clock framework, dvfs, and cpufreq driver s/w layers. To be used by system power supply over-current ISR. (cherry picked from commit fca2a12e90684526b2b7aeeb3af31de4254ad939) Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit b30bf0b313131037baffed7b6467eb1e0f021d19) Change-Id: Ice064326d46f868a9d59d2e1f53930d644fdfc02 Reviewed-on: http://git-master/r/64766 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: Rf42ae930ba90de1c40843b5565251e4c1c92a642
2011-11-30arm: tegra: Add HDA supportSumit Bhattacharya
Modify HDA device names to be inline with Intel HDA driver. Also add entries for both HDA controller memory base address and HDA controller PCI base address. Also modify the dev_id and con_id of HDA related clocks so that they can be used by HDA driver. Bug 872652 Change-Id: Ifa05fe7d3d524e9ae310594a0e582c297dc52ef7 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/59506 Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Rebase-Id: R098f861d94a78a1401841b71b8c591b902b7b0bc
2011-11-30ARM: tegra: clock: Update Tegra3 EMC clock configurationAlex Frid
- Moved initialization of Tegra3 dram configuration variables from EMC DVFS setup to EMC clock initialization, so that these variables can be used independently of DVFS. - Added graceful exit from EMC DVFS setup in case of empty DVFS table - Applied EMC minimum rate to direct EMC clock round rate operations (currently applied only to shared EMC bus update). (cherry picked from commit c6b3f6e0eb0b6e3485d02fc5306a1c09cbacf914) (cherry picked from commit cbf09d55bb9fa9c9ade7bb472859b4808f47b615) Change-Id: I84bbdc05ff7a0670ec9d088b98a9df25683db4df Reviewed-on: http://git-master/r/62029 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0fb03ff9903aa51aa922b4a49eed96aad0e97a06
2011-11-30ARM: tegra: clock: Clean miscellaneous Tegra3 clocksAlex Frid
- Removed xio and twc clock descriptors (no such clocks on Tegra3) - Updated 1.7GHz cpu frequency table (for T33), and added 1.5GHz table (for AP33) - Updated emc bridge related comments (cherry picked from commit 5749bd88bad0eb23cfc2d4fc721ae30ff5b9f5e0) (cherry picked from commit 06312525cb8021b73cd65993ff7e400e4fa9314d) Change-Id: Ia1502bf85e0e5121d0e536b56277659710c70d87 Reviewed-on: http://git-master/r/62027 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R4cde93c9ec39b7c1787235ddf99743b4874fb394
2011-11-30ARM: tegra: clock: Increased Tegra3 CPU maximum rateAlex Frid
Increased maximum rate of CPU clock sources, and added cpufreq scaling table to cover frequency range up to 1.7GHz for fast Tegra3 parts. Bug 841336 (cherry picked from commit 4bb23d23321e976f08bb05b37df80e2b7df5a09c) (cherry picked from commit ee9f100e74b7b6cf4428a1a7a66cc5f082fc6aae) Change-Id: I4009f777793a6b78862f4712fcba6f435699e4eb Reviewed-on: http://git-master/r/61709 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc1d6e48791296b07cab604843b65225a1b362dad
2011-11-30ARM: tegra: clock: Set Tegra3 2D/3D idle divisorsAlex Frid
Enable 2nd level hardware controlled clock gating. (cherry picked from commit 9dc6277e84a504d30dd5c07853301decf66c3060) (cherry picked from commit 0f5ec1901932d78796e143c730ebd9e3f4ffc397) Change-Id: I219a7fcd0e6ee47418cdd444cc101a1c6b266e1f Reviewed-on: http://git-master/r/61706 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R65f5ecab707df40f9e98e954420245c9a4a2c476
2011-11-30arm: tegra: rename tegra30 dam clocks to match dam driver's needsNikesh Oswal
Bug: 862023 Change-Id: Ib65ed2a54b4daf3ab91cbb826d8a1b661244d267 Signed-off-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-on: http://git-master/r/59864 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R9beac42bb660bfd8dcb122810594aae4aae2042f
2011-11-30ARM: tegra: power: Add Tegra3 balanced throttlingAlex Frid
Balanced CPU and core domains thermal throttling on Tegra3. When throttling is enabled the new algorithm caps core bus frequencies (EMC, cbus and sbus) along with CPU rate. The throttling steps, and time spent on each step are pre-defined based on characterization results. (cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e) (cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f) Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f Reviewed-on: http://git-master/r/61024 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190
2011-11-30ARM: tegra: clock: Add shared floor EMC/cbus/sclk usersAlex Frid
(cherry picked from commit 3c5a0b3d7bfbe30e1f312ae86d11eb8ee5bff7fa) (cherry picked from commit 1017145476f4467536fd133dc679d5947a35d299) Change-Id: I2968817f0148d10ca2f3fe14af018b2cc75d22da Reviewed-on: http://git-master/r/61022 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rb341188a0d72752b12e6137033c36cb892d9eb63
2011-11-30ARM: tegra: clock: Remove Tegra3 initial pll_m refcountAlex Frid
Removed Tegra3 pll_m refcount from common and board initialization. As a result pll_m is turned off when all client clocks are disabled. Added pll_m disable/enable control via PMC registers - this one actually works on Tegra3; kept clock register control in place, just in case. Originally implemented in dee91eaf47a7e6b392e9663170dcfdcdde73446c. Bug 888476 Change-Id: Ifa70d25ce8d93abc12c741d3a51b32110db3f7dd Reviewed-on: http://git-master/r/60129 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rf4201b6244e1dc202793730afa900a6b15b658b9
2011-11-30arch: arm: Enable SPDIF driver for Tegra30Sumit Bhattacharya
Bug 872652 Change-Id: Ic170dc2fc86f74d9e67d3b73a6f83368597dafcb Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/54975 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R96e76083f2cf154be6c450aff9005a0057bf5cb4
2011-11-30arm: tegra: clock: fix clk debugfs init by using duplicate clocksNitin Kumbhar
Clocks added for nvavp with same name result in a failure in debugfs_mknod() with EEXIST error when a node for a clock is being created in /d/clock/ directory. Resolve this by adding duplicate clocks for nvavp. Change-Id: I1caf8c50411cf5a9d3f285ee6c5e083f8d83c13c Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: http://git-master/r/55896 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Rebase-Id: R059dc1fe3b41f448ff01dc1aa257cacfdebeaea4
2011-11-30ARM: tegra: clock: Do not use PLLC for Tegra3 audioAlex Frid
Since PLLC is scaled with graphics c-bus clocks, Tegra3 audio clocks can not use it - remove PLLC option from audio clock mux. Change-Id: Ie5b727e4534962b846bd049ca02dc679607fe6fa Reviewed-on: http://git-master/r/55294 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rdf35727020f3cd57724d867283e0a2fee88aef16
2011-11-30ARM: tegra: clocks for nvavpSachin Nikam
Bug 880683 Change-Id: I806b7ad8f33d3067abf2a7b3f3098bb1d30f8778 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/54723 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R788f3fee92cab2e9872746d1b6b34cc759a4637d
2011-11-30arm: tegra: clock: Set i2c clock control to non-sleepableLaxman Dewangan
Configuring the i2c clock controls like clk_enable()/clk_disable() to non sleepable by removing the cansleep parents. bug 876130 Change-Id: I4a1d07d9282288addaea4b9f23d76703bf987da0 Reviewed-on: http://git-master/r/52819 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Rebase-Id: Rf544ff41484ce9eb7e8032414ca572007730ae65
2011-11-30ARM: tegra: clock: add low speed uart clocksJin Qian
K39 disable uart clocks in LP0 suspend with irq disabled so they cannot sleep. Add new uart clocks with low speed parents so that clk_disable doesn't sleep. Change-Id: I92109acff588591904f15dceac49acb89962ab9b http://nvbugs/876144 Reviewed-on: http://git-master/r/52215 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R7e184ad00f065747656272b4a9cac13a2a79d284
2011-11-30ARM: tegra: clock: convert tegra3 suspend/resume to syscore_opsJin Qian
Bug 862504 Change-Id: I5a1f3a7689f09e73b30e35b5f5ebb5773d0c0440 Reviewed-on: http://git-master/r/50090 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R87bf48392cc199b37d1f5ca272203a53b1d7b0c5
2011-11-30nvhost: power: Separate module shared clocksTerje Bergstrom
Register clocks that are shared amongst modules (emc, epp) as separate clocks. This way setting EMC clock for 2D does not interfere with EMC clock needs for 3D or MPE. Bug 868554 Original-Change-Id: I5c7dddc8f1d67969865918e577bd24b274d9e897 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/49603 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R6d25c0765bbaf73f50568b7438c3b4376befef9b
2011-11-30arm: tegra: clocks: add bsea to clk_duplicatesVarun Wadekar
bsea clock entry is needed by the tegra-aes driver to access the AES engine present in BSEA. Original-Change-Id: I3629f96e12c38f9cf6a45f5ae82a6c99c8cce9bb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/47721 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R20b31750fd34ba85b1a2a8b01390f3d3f7922301
2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I02a1f3a3d12d426748abaa11947b055a655ebfdf Reviewed-on: http://git-master/r/45454 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Rebase-Id: Raeb48e25187d8cc47c9418dffdcb7f770afac83b
2011-11-30ARM: tegra: dvfs: Update Tegra3 I/O dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I389484bcabd5546da55d851ec0b4ffbb82318a81 Reviewed-on: http://git-master/r/45453 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Rebase-Id: R05f71b759e1038eea0ed8743bad1f4f5d4309a98
2011-11-30ARM: tegra: power: Propagate Tegra3 EMC parent ref countAlex Frid
Since, Tegra3 low level suspend code may change EMC parent underneath clock framework ref count for the new parent is propagated up to the clock root during clock resume procedure. Bug 853986 Original-Change-Id: Iae84ee391e8940fc2d2fcfe47a7a3aae4faa6888 Reviewed-on: http://git-master/r/45712 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rcc48c9ee5b48d840a7886d80ed0dd30f8c4b6691
2011-11-30ARM: tegra: dvfs: Update Tegra3 VDE/VI/PLLs dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I470693d8d1bcf14ed519d769edbd11b1c714c944 Reviewed-on: http://git-master/r/44183 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R97845546c2eaaf601d01b3ea9934272ee5d761a8
2011-11-30ARM: tegra: dvfs: Update Tegra3 SCLK dvfs tableAlex Frid
Bug 817679 Original-Change-Id: I9ae7afbb2f11d26f5248b0071ba62659824a95fa Reviewed-on: http://git-master/r/44182 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rda0b1a55e7f41da44476547fe6dde8987c02c363
2011-11-30ARM: tegra: clock: Update Tegra3 SCLK divider selectionAlex Frid
Integrated the following limitation on 7.1 dividers setting when used as a source for system clock: no fractional settings are allowed with the exception of 1 : 2.5 ratio at core voltage 1.2V and above. Bug 840399 Original-Change-Id: I3a5f65c8d8112e2ffe98165f25f64fd385e2a5d4 Reviewed-on: http://git-master/r/44181 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R80eaf5c063f5fa116d178a6235c8d6f42fffa213
2011-11-30ARM: tegra: clock: Replace Tegra3 main clock disable bug with warningAlex Frid
On attempt to disable Tegra3 main clock generate WARN() rather than BUG(). Clock is not actually disabled in any case. Bug 853986 Original-Change-Id: I5bae24141f49beb02e50f7db37184ea80d526a28 Reviewed-on: http://git-master/r/43758 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R9a24c51dc6fde5c1f5d102747c5e32a3931be589
2011-11-30ARM: tegra: clock: Increased Tegra3 UART input frequency limit.Alex Frid
Bug 854841 Original-Change-Id: I924d48e1ef001b99d83ec5694200606e60e0013c Reviewed-on: http://git-master/r/43536 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R084584e22970c8613663deee91ad8d5eb392281c
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-02 01:09:21 +0000