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path: root/arch/arm/mach-tegra/tegra3_clocks.c
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2013-01-24tegra: apalis_t30: initial Toradex Apalis T30 L4T supportMarcel Ziswiler
Tested on early prototype Apalis T30 V1.0a module. Known issues: - ADC not integrated yet. - HDA not integrated yet. - CEC not integrated yet. - IrDA not integrated yet. - Keys not integrated yet therefore no way to wake from suspend. - 8-bit MMC1 slot card detection interrupt not working despite detection GPIO successfully being tested with GPIOConfig. Note: even 8-bit cards work fine if already plugged-in during boot. - PCIe limited to internal Gigabit Ethernet chip for now due to our proprietary way of resetting other ports which requires further integration into NVIDIA's driver.
2012-11-12Merge branch 'l4t/l4t-r16-r2' into colibriMarcel Ziswiler
Conflicts: arch/arm/mach-tegra/tegra3_usb_phy.c arch/arm/mach-tegra/usb_phy.c drivers/usb/gadget/tegra_udc.c drivers/usb/otg/Makefile drivers/video/tegra/fb.c sound/soc/tegra/tegra_pcm.c
2012-10-03tegra: colibri_t30: hack to avoid clock warningsMarcel Ziswiler
Hack to avoid extensive warnings being logged during boot-up due to CPU clock adjustments before regulator being ready.
2012-08-29i2c: tegra: rename fast clock and div clockLaxman Dewangan
Rename fast clock to "fast-clk" and div clock to "div-clk" in driver and clock table to have aligned with mainline as: This is based on change: --------- commit f16e6e77a105ec53496f0d8343895da342917873 Author: Laxman Dewangan <ldewangan@nvidia.com> i2c: tegra: pass proper name for getting clock --------- Change-Id: Ie9a1972a18e2e60ac7c84c4509860cf72405ef16 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/128150
2012-08-16ARM: tegra: clocks: Frequency stats for SCLK/CBUSSrikanth Nori
This adds a frequency histogram of the frequencies that SCLK and CBUS clocks go to over time. Stats are presented in the debugfs at /d/clock_stats/cbus and /d/clock_stats/sclk only if debugfs is enabled in config Change-Id: Icae83329612958d8ed4318b2e10c487683d9d734 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/118380 Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
2012-08-03ARM: tegra3: clock: Put graphic clks to safe rangeJong Kim
Initialize graphic and video input clocks in to safe frequency ranges. bug 966041 Change-Id: I48a035b42bad5a6d36f56e2b0610baf0703c3bcd Signed-off-by: Jong Kim <jongk@nvidia.com> (cherry picked from commit c33f503e768c44913af8d96898da43be05cdc01a) Reviewed-on: http://git-master/r/119792 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-07-30ARM: tegra3: clock: Put graphic clks to safe rangeJong Kim
Initialize graphic and video input clocks in to safe frequency ranges. bug 966041 Change-Id: I48a035b42bad5a6d36f56e2b0610baf0703c3bcd Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/117484 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-07-25ARM: tegra: clock: Add Tegra3 cbus profile capAlex Frid
Change-Id: I4d15ef7a9089bf3519155d9ccf5192bf3dcf0bd6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/116873 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-07-23ARM: tegra: clock: Set SCLK floor for CPU mode switchAlex Frid
Set SCLK floor to 80MHz for Tegra3 CPU mode switch. Bug 933984 Change-Id: Ibbb0a24cd763c11b3cead60efe26096bae3e6ddd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/106035 Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com> Tested-by: Jay Cheng <jacheng@nvidia.com> (cherry picked from commit 842f7ddb7a188e36a2ff153dc0d8ed38b5e28319) Reviewed-on: http://git-master/r/113981 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: Tegra3: clocks: Configurable cbus dividerMohit Kataria
Added config option to set cbus divider. Bug 978870 Change-Id: I49c57064ce695dd703ad97a50b8c0d373f5a05d0 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/114197 (cherry picked from commit 3f2b0e2b973a106d62e1f4bfb75bb40bd1a96b9b) Reviewed-on: http://git-master/r/109962 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-23ARM: tegra: clock: Reduce Tegra3 pll post-lock delayAlex Frid
Reduced pll post-lock delay from 50us to 2us. Rearranged wait for lock loop to delay first check of lock bit by 2us after pll is enabled. Added read fence for PLLM lock via PMC (in this case enable bit is in APB bus register, but lock detect bit is in PPSB bus register). Bug 1017271 Change-Id: Ibc963533854383e884d87be61e1b98e9d54d3ea0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115933 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-20ARM: tegra: clock: relax memory efficiency if 3d clock is offPeter Zu
Bug 1003509 Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206 Signed-off-by: Peter Zu <pzu@nvidia.com> (cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30) Reviewed-on: http://git-master/r/115468 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-17ARM: Tegra3: clocks: optional se.cbusMohit Kataria
Made se.cbus optional so that se clock can be derived from other clocks and not just from the clocks which drive cbus. Added config option for the same. Bug 978870 Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/110827 (cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de) Reviewed-on: http://git-master/r/106397 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-16ARM: tegra: clock: Add missed Tegra3 PERIPH_ON_APB attributesAlex Frid
Change-Id: I12be16dbc2614224ba852216a645d0f84c795334 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/115929 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-07-16ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tablesAlex Frid
Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum clock limits based on recent characterization results. Bug 817679 Bug 841336 Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Dynamically re-lock memory pllAlex Frid
So far Tegra3 EMC DFS allowed only scaling rates that can be divided down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM is always running at maximum SDRAM rate set at boot time, while PLLP rate 408MHz is fixed across all Tegra3 platforms. This commit implements dynamic re-locking of PLLM at run time. Now memory pll can lock either at boot rate or additional auxiliary rate that is selected as follows: auxiliary PLLM rate must be present in EMC DFS table, it must exactly match one of the rate steps for Tegra3 graphics bus with PLLC clock source (cbus), and must not be a proper factor of boot PLLM rate or PLLP fixed rate. When switching PLLM between boot and auxiliary rate, PLLC is used as backup memory pll, and during this time cbus is locked at auxiliary rate. In addition system bus is forced to temporarily use PLLP as a clock source (this is necessary as sbus main clock source is PLLM secondary divider PLLM_OUT1). Limitations: - only one auxiliary rate is supported, and it should be below PLLM boot rate, but above half of boot rate - dynamic re-lock is allowed only on LPDDR2 platforms - no clock other than EMC and system bus could use PLLM as a source; so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be selected, and VI clock (not covered by PLLM restricted configuration) must be moved to PLLP. Bug 1005576 Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/111438 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a) Reviewed-on: http://git-master/r/114760 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Allow Tegra3 PLLM rate changeAlex Frid
Allowed Tegra3 memory PLLM rate change, provided it is disabled. Since PLLM can deviate from boot configuration now, and on Tegra3 it is controlled by PMC override registers (not CAR module registers): - Re-factored PLLM initialization, resume, and set rate operations accordingly (enable and disable ops already used PMC override). - Made sure that boot configuration is restored on entry to LP0 to match memory timing saved in scratch registers. Bug 1005576 Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110937 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8) Reviewed-on: http://git-master/r/114759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record shared bus backup rateAlex Frid
Added shared bus backup rate entry to clock descriptor; initialized it for cbus (currently the only shared bus with backup source). Bug 1005576 Change-Id: I8124aa87f1dc307e42417da8f78797cfaf71e5dc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110934 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bc5ed688929c3c0ca920b5e9663cf9c6fb85c00f) Reviewed-on: http://git-master/r/114757 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Adjust Tegra3 cpu to emc ratioAlex Frid
On Tegra3 changed cpu rate threshold for maximum emc rate request from 750MHz to 925MHz. Adjusted cpu frequency table to provide entries close to the new threshold for all Tegra3 skus. Bug 998044 Bug 1003521 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I6e6df1958db9d55ad64cf35a5e9fe6ec74b8d4ea Reviewed-on: http://git-master/r/106946 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-06ARM: tegra3: clock: Add EPP clock for ISP channelSonghee Baek
Adding EPP clock is for using EPP to support rgb capture in ISP channel. Bug 988546 Change-Id: I7d02cccfd228a235a7eadd67ae3304757ce90360 Signed-off-by: Songhee Baek <sbaek@nvidia.com> Reviewed-on: http://git-master/r/108413 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-06ARM: tegra: clock: Add CEC clockAnkit Pashiney
Added CEC clock for tegra3 bug 894195 Change-Id: I7882371f3ab0f03454d372a7240acd9bd78c2c9c Signed-off-by: Ankit Pashiney <apashiney@nvidia.com> Reviewed-on: http://git-master/r/105518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2012-06-14ARM: tegra: resolve compilation time warningsSanjay Singh Rawat
- Adding flag to treat warning as error. - Handling warnings of unused variable, structures and functions, wrong return type, wrong type comparision. Bug 949219 Change-Id: I9d02387ce1073c4e46f69d01669285aa3754f1d9 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/104968 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-05-25Arm: Tegra3: clocks: Disabled SSCCENTER bit for plleMohit Kataria
Disabled SSCCENTRE bit for plle as per golden register (value provided by syseng) Bug 942384 978870 Change-Id: I3c2f8e8e220015b58f0c8bcbaac4e9998a5b6dcd Reviewed-on: http://git-master/r/98381 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/102408 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-25Revert "Revert "arm: tegra3: change min_rate for clocks""Hunk Lin
This reverts commit 18ed77b122dd1fbb9a6a5373da36ab32d0f0cee1. The noisy audio playback on Tegra3 with secure-OS issue is fixed by updating TL's SDK to 1.08. Change min_rate for clocks back to 12Mhz. Bug 939415 Change-Id: Ib0daf98faa85cc7cbc1dbfd4bf458427f914d830 Signed-off-by: Hunk Lin <hulin@nvidia.com> Reviewed-on: http://git-master/r/104317 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: clock: Account for memory BW efficiencyAlex Frid
Account for memory efficiency when processing requests from Tegra3 EMC shared bandwidth users. Do not round requests from these users until they are aggregated. The respective debugfs node: /d/tegra_emc/efficiency (in %). Bug 952739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084) Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458 Reviewed-on: http://git-master/r/103499 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-21ARM: tegra: clock: Share Tegra3 camera EMC bandwidthAlex Frid
Change Tegra3 camera EMC shared user mode from SHARED_FLOOR to SHARED_BW and combine requests from ISO clients (camera and display, which is already in SHARED_BW mode). Bug 652739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit f1107ea4fe229d9807c1fba79a003753d0a8be7f) Change-Id: If5b7f578060a646df1794dde8c9be2944d88e942 Reviewed-on: http://git-master/r/103498 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-14arm: tegra: clock: Add tegra3 sdmmc4 EMC shared userPavan Kunapuli
Adding tegra3 sdmmc4 EMC shared user in the tegra3 clock table. Bug 967719 Change-Id: I934dcaebf664f8b1db9ea07eef07eb6f266822aa Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-on: http://git-master/r/100582 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-06arm: tegra: update the udc driver nameRakesh Bodla
Update the clocks structure to use new udc driver name. Also, update the device structure. Bug 887361 Change-Id: I0fd846ab177e8651f285bcb9796361d30967b830 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/99448 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-05-03ARM: tegra: clock: Add DSI implicit dependency on PLLPAlex Frid
Added dsi fixed clock entry derived from PLLP_OUT3. This would allow DC driver to properly ref-count implicit dependency of DSI operations on PLLP_OUT3 clock. Bug 933653 Change-Id: I71e6ada13f9d231c5a4924f345cdbf7cf05cd59e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/98103 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-05-02Revert "arm: tegra3: change min_rate for clocks"Amit Kamath
This reverts commit 5dc206986103aaa443fa6b0ef6fef20bcb35d299 because it causes noisy audio playback on Tegra3 platforms with secure-os. Bug 939415 Change-Id: Ib19962dd57a2560945d1c0ed49b3eade2c751446 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/98986 Reviewed-by: Automatic_Commit_Validation_User
2012-04-19arm: tegra3: change min_rate for clocksAmit Kamath
Set minimum sclk,pclk and hclk rate same at 12Mhz for power optimization bug 939415 Change-Id: I579eeca780357b02f65333ffea58301040943506 Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/96922 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-19ARM: tegra: remove T30 FPGA supportJuha Tukkinen
Remove T30 FPGA support as it will conflict with downstreaming mainline way of using chipid and revision. Change-Id: Ic1fd1107801de13c265c7dde8571e0537c43f4fd Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/95872 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-04-17ARM: tegra: clock: Apply shared bus ceiling alwaysAlex Frid
Apply shared bus ceiling regardless of whether Tegra3 SHARED_CEILING user is enabled or disabled. Thus, we no longer need to enable ceiling user - and the bus itself via child-parent relations - to cap the bus rate. Bug 954896 Change-Id: I7f96f03f05fd39334c9ee977cd1ac18d86a1fc0d Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 07b1a707aa14dcab37f095a3bb78af79a54c399b) Reviewed-on: http://git-master/r/95739 Reviewed-by: Daniel Solomon <daniels@nvidia.com> Tested-by: Daniel Solomon <daniels@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-04-03arm: tegra3: change min_rate for sclkAmit Kamath
Change the minimal rate of sclk to 12 MHz and set the lowest frequency of sbus to be 40 MHz when display is on. bug 939415 Original change http://git-master/r/#change,76959 Change-Id: I81cda6a95494764721c1be5b4001c476f3aed6ab Signed-off-by: Amit Kamath <akamath@nvidia.com> Reviewed-on: http://git-master/r/93850 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-26arm : tegra: clocks: Add PERIPH_ON_APB flag for apbif clockSumit Bhattacharya
Bug 953357 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/90845 (cherry picked from commit 24b715551882d387b82a89e0213012863e46bb95) Change-Id: Ia8632fccab0708dacd9ef4b9360f8ef499b47818 Reviewed-on: http://git-master/r/92280 Tested-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Peterson <speterson@nvidia.com>
2012-03-20ARM: tegra: clock: Update parameterized cluster switchAlex Frid
Adjusted CPU rate during parametrized (enforced from sysfs) cluster switch, so that target rate meets min/max constraints on both sides of the switch. Updated local timer rate accordingly. Bug 945975 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit c27f5a2e7380cb667f1f6a4ba61daf67c63ef2d4) Change-Id: I130ec1a32ecaf8adfd7eff1ec2042f569b54ac54 Reviewed-on: http://git-master/r/90805 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-19ARM: tegra3: dvfs: Changed max values of clocksMohit Kataria
Changed clock frequency of some clocks as per Automotive POR. Bug 882186 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/75210 (cherry picked from commit 9cc17e9cddfedc6fe977f103c5e21ae3f82c3496) Change-Id: Ibb0e79e75c2fca7d9f09d373c163ef08cc636819 Reviewed-on: http://git-master/r/90490 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-15ARM: tegra: clock: Entry for spi-sclk clock controlLaxman Dewangan
Tegra's spi requires some minimum sclk clock frequency for proper functioning. Making entry for spi-sclk clock so that spi driver can get the proper clock for controlling the minimum rate of sclk. bug 949393 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/89524 (cherry picked from commit 542cbe457b1b19b8fdf8cbf193e38a00027060c2) Change-Id: I3f829b36b1b42bb8b1c6e4e21745855e113c17c1 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/90294 Reviewed-by: Automatic_Commit_Validation_User
2012-03-14ARM: tegra: clock: Update Tegra3 CPU suspend rateAlex Frid
Set Tegra3 CPU suspend entry rate to maximum LP mode rate - speed up suspend, and still allow to switch to LP CPU mode on suspend entry. Bug 946301 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5e7fa33ebcb5602093f9bf86e37f0478e389c633) Change-Id: I5df4305579a9992817bae168925c4bb208934481 Reviewed-on: http://git-master/r/89351 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-03-06ARM: tegra: clock: Put Cardhu clocks to known stateJong Kim
Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and audio clocks into known state, so that L4T Cardhu works on u-boot. BUG 931602 Change-Id: I7c5aaff340a072fe6587822eccc89df72b2b1d79 Signed-off-by: Jong Kim <jongk@nvidia.com> Reviewed-on: http://git-master/r/86725 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-28arm: tegra: enterprise: add 12.75mhz memory freqWen Yi
Add operation parameters for running emc at 12.75 MHz into emc dvfs table. Bug 922351 Bug 943239 Signed-off-by: Wen Yi <wyi@nvidia.com> Reviewed-on: http://git-master/r/79577 (cherry picked from commit 98f225dae75c8ed04cd11d0f6514f5259f3b9a9b) Change-Id: I98d972e76a988d167a214ddaac800a5a442f01c3 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: http://git-master/r/86298 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-23ARM: tegra: clock: Update secondary pll dividers resumeAlex Frid
During resume from LP0 on Tegra3 always enable pll secondary dividers before clocks restoration (to make sure clock sources are enabled). Restore actual secondary dividers settings after clocks are restored. Remove pllp secondary dividers restoration from cpu complex restore, and add them to common clock restoration procedure. These dividers are not affected by CPU complex suspend, only by LP0 core suspend. Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 1f631436717c0602ef30770f7976615150114afe) Change-Id: I45777ca0535f51a39c35e9d360ac6e97a13ea92c Reviewed-on: http://git-master/r/84712 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-02-21ARM: tegra: clock: Support for clock source control without enable bitLaxman Dewangan
Some of controller like i2c requires a different clock source which is not enabled/disabled by the clock bit in CAR register set. Handling such cases by looking for PERIPH_NO_ENB flag when calling clock enable/disable functions. Change-Id: Id0d1df7946d1c83d769116ae7a91546bd59d4478 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/84709 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-21ARM: tegra: clock: Add i2c fast clock entryLaxman Dewangan
Adding i2c fast clock entry which is derived from pllp_out3. This is non-muxed input clock for i2c and does not have any enable bit on CAR register set to enable/disable through clock-reset registers. bug 933653 Change-Id: I0c50d6570b88510e3acef2ed0993e4305b2e34e8 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/84693 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-17Revert "arm: tegra3: change min_rate for sclk"Chandrakanth Gorantla
This reverts commit a61ef84d7746134aae316fa76867d69fc0753880. Bug 939415 Change-Id: I7d7c2a69ac7261a221cf69b8f8981d42f575f789 Signed-off-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-on: http://git-master/r/84025 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-15ARM: tegra: clocks: Consolidate input frequency measurementsScott Williams
Consolidate the functions used to measure the input frequency into a single implementation and perform the measurement only once. Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-14Revert "ARM: tegra: clock: Add i2c fast clock entry in shared clock"Simone Willett
This reverts commit 0fbe4ffbcd3fcff93cc574d2bbea94e9971c79cf Change-Id: Iea7bdd09565d5de8e004db2b8e5e3fbb3b958531 Reviewed-on: http://git-master/r/83847 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-02-14ARM: tegra: clock: Add i2c fast clock entry in shared clockLaxman Dewangan
Adding i2c fast clock entry which is derived from pllp_out3. bug 933653 Change-Id: I5c799edecec7ee7060ff2a11cf1cb22a1c702e26 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/78995 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-02-03ARM: tegra: dvfs: Add Tegra3 x7 core dvfsAlex Frid
- Added Tegra3 x7 core dvfs entries - Increased EMC, graphics, and UART clocks maximum limits - Updated PLLC configuration table Bug 841336 Reviewed-on: http://git-master/r/76942 Change-Id: Ifa235e60d66d959ad589574c5ebde90eb0b65385 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78707 Reviewed-by: Automatic_Commit_Validation_User
2012-02-03ARM: tegra: clock: Expand PLL usage restriction mechanismVarun Wadekar
Expand PLL usage restriction mechanism from Tegra3 only to common tegra clock framework implementation: fail set parent API if new parent is not allowed per usage policy. Actual usage policy is architecture dependent and exists now only on Tegra3. Reviewed-on: http://git-master/r/77251 Change-Id: I2a8d60cc0ddfd2179961ef50418b193f2e1829c8 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78029 Reviewed-by: Automatic_Commit_Validation_User
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-11 15:14:32 +0000