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2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: Idd5fbdc14a3e2ff10c2636da0465eab6ab486fb9 Reviewed-on: http://git-master/r/47392 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R5f3608dba861d40c6d4257f2694de63a4202a6ff
2011-11-30ARM: tegra: dvfs: Update vdd_cpu/vdd_core dependencyAlex Frid
Updated vdd_core dependency on vdd_cpu: core-above-cpu margin is now different for different ranges of vdd_cpu (was flat 0). Bug 860893 Original-Change-Id: Ib62793542957a3b9b4b6b8a41d63f7b3516ac09f Reviewed-on: http://git-master/r/45926 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R490b997c3a945bb61c056ee0c22c556d203b1b2c
2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I651ec1004794641c3b6df8b943fbb071699dabe1 Reviewed-on: http://git-master/r/46149 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R5a16e04b7b7b321a15b6282998fd7029d2f678c2
2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I02a1f3a3d12d426748abaa11947b055a655ebfdf Reviewed-on: http://git-master/r/45454 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Rebase-Id: Raeb48e25187d8cc47c9418dffdcb7f770afac83b
2011-11-30ARM: tegra: dvfs: Update Tegra3 I/O dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I389484bcabd5546da55d851ec0b4ffbb82318a81 Reviewed-on: http://git-master/r/45453 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Rebase-Id: R05f71b759e1038eea0ed8743bad1f4f5d4309a98
2011-11-30ARM: tegra: dvfs: Update Tegra3 VDE/VI/PLLs dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I470693d8d1bcf14ed519d769edbd11b1c714c944 Reviewed-on: http://git-master/r/44183 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R97845546c2eaaf601d01b3ea9934272ee5d761a8
2011-11-30ARM: tegra: dvfs: Update Tegra3 SCLK dvfs tableAlex Frid
Bug 817679 Original-Change-Id: I9ae7afbb2f11d26f5248b0071ba62659824a95fa Reviewed-on: http://git-master/r/44182 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rda0b1a55e7f41da44476547fe6dde8987c02c363
2011-11-30ARM: tegra: Remove write permission for sysfs attrSachin Nikam
CTS File permission test expects there shoudn't be any writable permission for Group and Others for any file in kernel. Bug 840409 Original-Change-Id: I277e1e8d22f19899935336f2322f8bd4b46a9f85 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/41522 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com> Rebase-Id: R22e200ca6f17c9058a5739de28a9e47ca0391b40
2011-11-30ARM: tegra: power: Add Tegra3 sysfs core cap interfaceAlex Frid
Added Tegra3 sysfs throttling interface for VDD_CORE domains: /sys/kernel/tegra_cap/core_cap_level - common cap level for all core shared buses: emc (memory), sbus (system clock), and cbus (graphics clocks). Cap level is specified in millivolts, and maximum rate limits from the respective dvfs tables are applied to all bus clocks. Note that cap level affects only bus frequencies. Core voltage is not necessarily set at the cap level, since CPU and/or fixed peripheral clocks outside the buses may require higher voltages. /sys/kernel/tegra_cap/core_cap_state - provides enable/disable control of cap level throttling effect. Updated system clock dvfs table (new data better matching cap levels). Bug 837005 Original-Change-Id: I77b1d1c95ba623dcfb3f8290ec686e181558b84a Reviewed-on: http://git-master/r/40778 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rfab75e46ceaf2f1ad29ec91d946b50f1fd8a58d7
2011-11-30arm: tegra: dvfs: add fuse_burn to the dvfs tableVarun Wadekar
Bug 796825 Original-Change-Id: I8835427940905d90ca04955b5efe1605761c5554 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/38403 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R3dc69edfa374a47bcdd35e7acfd85d98ca7d66dc
2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU and core voltage dependenciesAlex Frid
Updated implementation of CPU and core voltage dependencies so that range limits can be changed for different versions of Tegra3 (rather than use fixed limits across entire Tegra3 architecture). Decoupled safe VDD step definition from range limit, and changed the step from 300mV to 100mV. Bug 841286 Original-Change-Id: I63e0bc9751048741a47a40410b54863984f91aca Reviewed-on: http://git-master/r/38179 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R665a6f859aa744e1b64a19d9ba5aa2f37581103e
2011-11-30ARM: tegra: dvfs: Set Tegra3 EMC max rate at 1.0V to 408MHzAlex Frid
Bug 836260 Original-Change-Id: I381619f6084a558f4c16142f8f0dfa3565ca2e94 Reviewed-on: http://git-master/r/39247 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Mandar Potdar <mpotdar@nvidia.com> Rebase-Id: R0d2d4bd478f526d116a741916de5c2fc2df7a998
2011-11-30ARM: tegra: clock: Synchronize Tegra3 clocks scalingAlex Frid
On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are sourced from PLLC through integer dividers. Low resolution of these dividers does not allow to set scaling frequency levels matching intermediate voltage steps within core voltage range. Only changing the source frequency can achieve it. However, re-locking common PLL while engines are running requires synchronization of engines clock control, and complex operations including switching to backup sources during PLL stabilization time. This commit introduces a new virtual clock "cbus" to support clocks synchronization and PLLC re-locking procedures. The dvfs table for cbus clock is constructed from frequency steps close to maximum rates for each characterized core voltage level. Engine clocks exposed to the drivers are no longer physical module clocks, but shared cbus users. Setting the rate for such clock specifies the clock floor. The final cbus rate is determined as maximum floor setting for all enabled engines, and rounded up along the cbus dvfs ladder. Actual engine clock rate is set equal to the cbus clock rate. Hence, engines will be running close to maximum frequency for minimum voltage that satisfies all floor requests. Special case: Host1x. This clock will be always configured at 1/2 of cbus clock rate, and its shared user floor request is ignored by cbus target frequency calculations. Added cbus dvfs tables and updated VDE engine dvfs data. Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6 Reviewed-on: http://git-master/r/36199 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915
2011-11-30HACK: tegra3: limit CPU DVFS to 'safe' valuesDan Willemsen
Rebase-Id: Rb8c6bb9a9766387feb8d4c1a6b9d55d0cc8d8c56
2011-11-30HACK: tegra3: disable Core DVFSDan Willemsen
Rebase-Id: R11032fbfc6b2c722655d40df54e3e49a1a492926
2011-11-30ARM: tegra: dvfs: Update DVFS tables with data for T30SDiwakar Tundlam
Change-Id: I38b9752adc9e927935fe7ffe5590c41577a45809 Reviewed-on: http://git-master/r/34381 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R318f6916f8213c25092110a8800eb506d1718b38
2011-11-30ARM: tegra: clock: Set speedo_id according to actual fused SKUDiwakar Tundlam
- Read SKU_INFO fuse to get A02 SKU info - Update CPU DVFS to use actual SKU info obtained - Enable main table for EDP capping and thermal throttling Original-Change-Id: I7ff3b06476998d77cc3f7a4fc03fb72e26b570db Reviewed-on: http://git-master/r/32084 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re91f616032d8045ea2c28822e40f815f3e449931
2011-11-30ARM: tegra: power: Update Tegra3 core dvfs tablesAlex Frid
Updated Tegra3 core dvfs tables with new characterization data. Respectively raised maximum frequency limits for CPU in LP mode, VDE/MPE/3D/2d/Epp and system bus clocks. Original-Change-Id: I79b58e482005896d55219e4fb9b9421f37dd46a1 Reviewed-on: http://git-master/r/32066 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R5e1c897eb4b1b8f3471fe7bd350ec5a8f378cb5d
2011-11-30ARM: tegra: clock: Set Tegra3 CPU maximum rate to 1.4GHzAlex Frid
- Added CPU DVFS tables for Tegra3 chips with 1.4GHz support - Updated speedo thresholds for process corners - Set Tegra3 CPU maximum rate to 1.4MHz. Effective only on boards with EDP table. Otherwise, the default EDP limit keeps rate below 1GHz. Original-Change-Id: Iaca3bb6a5fbfa1bf76131f49d08162fdbe35143f Reviewed-on: http://git-master/r/31887 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R6f077fe6e698d3b4fa7ed475e1926de648208e18
2011-11-30ARM: tegra: power: Enable Tegra3 core DVFSAlex Frid
Enable Tegra3 core DVFS with default EDP limit set to 1.2V. Bug 812738 Bug 826200 Original-Change-Id: If1e9f431729d0dbe6e8c89d9d8b9d5f9d2e8a2bf Reviewed-on: http://git-master/r/31254 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R3f6a3633f77b33541171c28078401a0fa51b432c
2011-11-30ARM: tegra: power: Update Tegra3 CPU DVFS tableAlex Frid
Original-Change-Id: I3164bb2d86619b891a647b5e6550470c509eb403 Reviewed-on: http://git-master/r/31308 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R956cf61f5689a91b58698a3c08c4f499c49fea71
2011-11-30ARM: tegra: power: Limit Tegra3 CPU nominal voltageAlex Frid
Limit Tegra3 CPU nominal voltage in case when maximum rate specified in the clock tree is below maximum rate in CPU dvfs table. Original-Change-Id: Ie7b47a1f482f3c33da19e530b05663683bd807a1 Reviewed-on: http://git-master/r/31307 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R08f5bb4d0d4c708078e067a24b4915b65a862964
2011-11-30ARM: tegra: power: Add out-of-range CPU dvfs entryAlex Frid
Original-Change-Id: Ic50e6261e34caa3851ef68a6e2a6cbbd600a13d6 Reviewed-on: http://git-master/r/30929 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R1782d94073db37818e6939e07d68a2de7a14daef
2011-11-30ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltageAlex Frid
For different Tegra3 process corners/skus/revisions/boards set nominal voltages for CPU and core rails as well as adjust maximum clock rates as follows. - VDD_CORE rail nominal voltage: default value is indexed by speedo_id of the chip (speedo_id is determined by chip sku and revision). Minimum of the default and board specific electrical design voltage is rounded down against core dvfs voltage ladder. The result is set as nominal core voltage (edp voltage API is not implemented, yet). - VDD_CPU rail nominal voltage: default value is indexed by speedo_id of the chip. If too high, it is lowered to core nominal voltage so that core_on_cpu dependency is resolved at nominal core level. The result is compared with voltage required to reach CPU maximum rate as specified in the dvfs table for the particular process corner. Again, the minimal level is selected, and finally set as CPU nominal voltage. After nominal voltages are determined, maximum rate for each dvfs clock is adjusted accordingly, so that it does not exceed the rate specified in the respective DVFS table at nominal level. Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3 Reviewed-on: http://git-master/r/30928 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: R30393515042d199154ba708afaefb134402f551a
2011-11-30ARM: tegra: power: Update Tegra3 core DVFS tablesAlex Frid
Updated Tegra3 core DVFS tables with characterization results. Changed default maximum limits for: sdmmc2/4 to 104MHz, vi to 300MHz, and hdmi to 148.5MHz. Original-Change-Id: Icd07d933d7d2f8c77d6e023b19b62e7ee3fc775a Reviewed-on: http://git-master/r/30551 Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R5f18b6b548c5093828804977b708d60a8da607ca
2011-11-30ARM: tegra: power: Add Tegra3 CPU/CORE rails dependenciesAlex Frid
On Tegra3 VDD_CPU must be within [VDD_CORE - 300, VDD_CORE] range. Updated tegra dvfs accordingly, and resolved circular dependencies between CPU and CORE rails created by this requirement. Original-Change-Id: I9c332ca2b4f4ed1599cb0712eb3eca55a1fa1539 Reviewed-on: http://git-master/r/29935 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: R6aa2bc61513ab16c4551ebeb193e01803501f596
2011-11-30ARM: tegra: power: Add Tegra3 core DVFS sysfs controlAlex Frid
Original-Change-Id: I085d8cff2b5fea60f5245c36eefe849aa17a58f5 Reviewed-on: http://git-master/r/29764 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R51b2ad284917e399000dde3a7094e0c7c3732102
2011-11-30ARM: tegra: power: Expand Tegra3 core DVFS tableAlex Frid
Expand Tegra3 core DVFS table with characterization results (core DVFS is still disabled). Original-Change-Id: Ic3b63192982312b722dd68ecd15e28d01b67a2f2 Reviewed-on: http://git-master/r/29763 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7f88f30ef5a0906d72b80b8f44c774aed008343d
2011-11-30ARM: tegra: power: Use conservative DVFS table for 800-1000mVDiwakar Tundlam
This reverts commit 3b657267b52a468f00b607670dcd3b1668b7cd3f. Original-Change-Id: I77b958c598275b6059961341f3cf1b5ef87e6f91 Reviewed-on: http://git-master/r/26952 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I193bad1dd70704bd7c3fd259943ccd2710f7d09b Rebase-Id: R86e8b3ecaea952d09ad0475d3b67d1e77b0f8523
2011-11-30(PARTIAL) ARM: tegra: power: Disallow LP2 when regulator is updatingDiwakar Tundlam
Original-Change-Id: I8012de82dfd4c47628fb202ba5ba98f3d199035f Reviewed-on: http://git-master/r/26630 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I17065422392d01509d2a745f2cb5d188450e32cb Rebase-Id: R6f46d3aca8a65798d1fcb7e1f60461c32ae1f99d
2011-11-30ARM: tegra: power: Split Tegra3 CPU-G and CPU-LP dvfsAlex Frid
On Tegra3 CPU power is supplied by different rails in G-mode (VDD_CPU) and LP mode (VDD_CORE) - updated dvfs dependencies respectively. Original-Change-Id: Ifae8ae501b227a44e46ce1577bcd532e2e778322 Reviewed-on: http://git-master/r/25200 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I96e6cb7e3dcdf8514714d2900d8f947b6438c95f Rebase-Id: R4d16a0002c701f6ee2f0f8c0f66c5313e4546d53
2011-11-30ARM: tegra: power: add cpu-dvs table for tegra3Diwakar Tundlam
Original-Change-Id: I3eac69eec691e4e75d698011461e578324fb4c1d Reviewed-on: http://git-master/r/23094 Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I9553f03a1947015c7a19c13eb2881835e04a5614 Rebase-Id: R102e04f03b7eee26739cb5c8bdec99c88bb53413
2011-11-30[ARM/tegra] Add Tegra3 supportScott Williams
Bug 764354 Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046 Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081 Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-11 22:57:25 +0000