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2012-07-30ARM: tegra: dvfs: Adjust VDD_CPU to offset agingAnshul Jain
Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-25ARM: tegra: clock: Add Tegra3 cbus profiling sysfs nodesAlex Frid
Added: /sys/kernel/tegra_cap/cbus_cap_level /sys/kernel/tegra_cap/cbus_cap_state Change-Id: I06a32ea4001f1f644da4f230870f39523f9b6df3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/116874 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com>
2012-07-24arm: tegra: dvfs: update AP37 dvfs entryRakesh Iyer
Update Tegra3 AP37 dvfs table entries. Bug 841336 Reviewed-on: http://git-master/r/115509 (cherry picked from commit fda92ca92eb421b554fcb50117c92ec59b4b515a) Change-Id: Ib15ba4731f0770a8af2272c51a90c7dc0fd8f6b9 Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/117926 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-20ARM: tegra: dvfs: add back 916mV & 1007mV entriesPeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/113751 (cherry picked from commit 833f9d47a350358000e9201f77a3c9fd655d2900) Change-Id: I679093d9d2577625bff3e02e25ffe90d396ea5a6 Reviewed-on: http://git-master/r/116134 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-20ARM: tegra: dvfs: update Tegra3 single-core dvfs tablePeter Zu
Bug 841336 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/110587 (cherry picked from commit c0e7904245168cafc426219948ab132a4d832376) Change-Id: I370f4af1d4ce888ebc71351519c1018b82d91913 Reviewed-on: http://git-master/r/116132 Tested-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-07-19ARM: tegra: dvfs: Handle Tegra3 alternative dvfs errorsRohan Somvanshi
Propagate error to the caller when switching between alternative cpu dvfs tables. Change dvfs table during cpu hotplug operation only after the new edp limit is set, and abort bringing cpu core on-line in case of failure in applying new (less conservative) table. When cpu core is removed change dvfs table before setting new edp limit, and ignore error (it is safe to continue with more conservative table). Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 951710ec179fd620a2251d0815ca7bff15da014b) Change-Id: Ib1ad8e41093fb9bee75d3d6bd18d0ac406da8271 Reviewed-on: http://git-master/r/114779 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-16ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tablesAlex Frid
Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum clock limits based on recent characterization results. Bug 817679 Bug 841336 Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107780 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-03ARM: tegra: dvfs: Update Tegra3 dsi dvfs tablesRakesh Iyer
Updated entries in Tegra3 dsi dvfs tables with recent characterization results. Bug 985671. Bug 1006163. Change-Id: Ife87f3ccfd9d6147d4aa5b57c1a5750bbabc7e6b Signed-off-by: Rakesh Iyer <riyer@nvidia.com> Reviewed-on: http://git-master/r/112805 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Zu <pzu@nvidia.com>
2012-06-18ARM: tegra: dvfs: Fix error checking of voltageJuha Tukkinen
Fix error checking of predicted voltage. Also get rid of maybe-uninitialized warning when using 4.6 toolchain. Bug 949219 Bug 999222 Change-Id: I47553aba5a93c91bdd93cbf75081d69f92aec4dd Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/108899 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-14ARM: Tegra: Enable 900MHz at 1V on restricted pll_mGraziano Misuraca
Allow pll_m to reach 900MHz at 1V on T30, T33, T37 rev A02+ SKUs. Bug 891320 Change-Id: Idbfb10014ae2a1d06abc3bc1d0bed59c583fac98 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-on: http://git-master/r/103453 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-14ARM: Tegra: cardhu: Let emc to 450MHz on T33+ at 1VGraziano Misuraca
Change dvfs table to allow emc to hit 450MHz at 1V VDD_CORE. Line in emc table is also used for T30/T30s but because those can't reach 1350mV they should never use a 450MHz bct and therefore jump from 400@1V to 800@1.2V as before. Bug 973238 Change-Id: I4f1f96c959658e6f9aeca8841c2bfa86fe20cfb8 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Reviewed-on: http://git-master/r/101868 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-14ARM: tegra: dvfs: Update Tegra3 I/O dvfs tablesAlex Frid
Updated 0.95V entries in Tegra3 dvfs tables for nand, nor, spi, and pwm clocks with recent characterization results. Removed usb, pcie, and spdif dvfs since characterization allows running these interfaces in the entire supported voltage range. Bug 817679 Bug 841336 Change-Id: Iaaa2a3ff8b3c07915f1cb05e7b14da545428888e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107779 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-06-14ARM: tegra: dvfs: Update Tegra3 display subsystem dvfs tablesAlex Frid
Updated 0.95V entries in Tegra3 dvfs tables for display and dsi with recent characterization results. Removed hdmi and crt dvfs since characterization allows running these modules at max rate in the entire supported voltage range. Bug 817679 Bug 841336 Change-Id: I28651a692e30a20536613460ea0e45155a530af7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107778 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-06-14ARM: tegra: dvfs: Update Tegra3 sclk and cbus dvfs tablesAlex Frid
Updated 0.95V entries in Tegra3 dvfs tables for sclk and cbus clocks with recent characterization results. Bug 817679 Bug 841336 Change-Id: I892690aea4c584b34be5dbfcbcd8b35abd86a997 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/107777 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-06-07ARM: tegra: dvfs: Separate Tegra3 single core dvfs tableAlex Frid
On Tegra3 added mechanism to alter dvfs table between single and multiple CPU cores. This mechanism is dormant since no single-core table is available yet. Change-Id: I63bd513bd5fd7347f64c88f46974cf7fac55c419 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/105508 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-07ARM: tegra: dvfs: Alter CPU dvfs on EDP eventsAlex Frid
Extended EDP processing of cpu up/down events with calls to alter CPU dvfs table. This is in addition to already supported changing of CPU dvfs on EDP thermal event. For now, added calls do not actually alter the table. Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/104883 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-07ARM: tegra: dvfs: Re-factor CPU alternative dvfsAlex Frid
Removed alternative frequencies table from dvfs structure, and replaced it with table pointer to facilitate future support for multiple alternative tables. Actually supported alternative dvfs table (Tegra3 CPU cold zone table) is not changed. Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/104882 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-04arm: tegra: resolve compilation time warningsSanjay Singh Rawat
Bug 949219 Change-Id: I91a67d30869e9800c483f112d58b9f76e2dbe361 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/103534 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-05-16Arm: p1852: dvfs: Added ASIC SKUs as per updated PORMohit Kataria
Automotive platforms are broken down further into 5 Asic skus from 3 ASIC SKUs, updated kernel to reflect these changes. Bug 983555 Change-Id: I75925c5853d4ec2a5c72e430f4c2380e58aae774 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/101903 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2012-05-08Arm: tegra: p1852: Avp clock frequency to 334Mohit Kataria
changed the max avp clock from 378MHz to 334MHz as per new POR changes Bug 883565 Change-Id: I4e9dda0288f3f85c8b1705971bb8f389127cff28 Reviewed-on: http://git-master/r/97279 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/100870 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-17ARM: tegra: clock: Apply shared bus ceiling alwaysAlex Frid
Apply shared bus ceiling regardless of whether Tegra3 SHARED_CEILING user is enabled or disabled. Thus, we no longer need to enable ceiling user - and the bus itself via child-parent relations - to cap the bus rate. Bug 954896 Change-Id: I7f96f03f05fd39334c9ee977cd1ac18d86a1fc0d Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 07b1a707aa14dcab37f095a3bb78af79a54c399b) Reviewed-on: http://git-master/r/95739 Reviewed-by: Daniel Solomon <daniels@nvidia.com> Tested-by: Daniel Solomon <daniels@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-26ARM: tegra: dvfs: correct LCD frequency for 1VRay Poudrier
Bug 841336 Reviewed-on: http://git-master/r/82996 (cherry picked from commit 5850c8f4968fd7acbb22e377a56a476e37ac5117) Change-Id: I61d5c1576a6f5caf82b3efec2123c47eb64889b2 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/88865 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-03-21Revert "ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1V"Alex Frid
This reverts commit db462754240e2ee6cf85e1253b1475a330ea0dfe - temporary work-around for bug 870300 is no longer needed. Change-Id: I3b76c01eef89cd80134210926e6623f0494626dd Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/89874 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-19ARM: tegra3: dvfs: Changed max values of clocksMohit Kataria
Changed clock frequency of some clocks as per Automotive POR. Bug 882186 Signed-off-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-on: http://git-master/r/75210 (cherry picked from commit 9cc17e9cddfedc6fe977f103c5e21ae3f82c3496) Change-Id: Ibb0e79e75c2fca7d9f09d373c163ef08cc636819 Reviewed-on: http://git-master/r/90490 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Mohit Kataria <mkataria@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-02ARM: tegra: dvfs: Update T30L and T30SL Vcore min values.Gaurav Sarode
Update T30L and T30SL values Vcore min voltage is now 1.2V when Vcpu >= 1.1V. Old setting was 1.3V. Bug 841336 Signed-off-by: Gaurav Sarode <gsarode@nvidia.com> Change-Id: I35202189618cffd4ead1fae3db462c3e970a7ed8 Reviewed-on: http://git-master/r/86912 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-15ARM: tegra: dvfs: Fix Tegra3 cbus limit at 1.35VAlex Frid
Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit e031d09197f7b4214ad035b1acf7d6c39049021e) Change-Id: Ie3dc75aa2997c52b7e5aa80c35165c8c4284b8ec Reviewed-on: http://git-master/r/83288 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-09ARM: tegra: dvfs: Expand Tegra3 cpu dvfs tablesAlex Frid
Expand Tegra3 cpu dvfs tables to add characterization results for 800mV VDD_CPU. Bug 817679 Bug 841336 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/77936 (cherry picked from commit f5b488019895c83e05ded8a8912cf3eb4eea5686) Change-Id: Id7e5a46c96c67ca80f552b742cf3cf341bb8e1f0 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: http://git-master/r/80000 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-02-03ARM: tegra: dvfs: Add Tegra3 x7 core dvfsAlex Frid
- Added Tegra3 x7 core dvfs entries - Increased EMC, graphics, and UART clocks maximum limits - Updated PLLC configuration table Bug 841336 Reviewed-on: http://git-master/r/76942 Change-Id: Ifa235e60d66d959ad589574c5ebde90eb0b65385 Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78707 Reviewed-by: Automatic_Commit_Validation_User
2012-02-03ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entriesAlex Frid
Bug 841336 Reviewed-on: http://git-master/r/76912 Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78706 Reviewed-by: Automatic_Commit_Validation_User
2012-01-20ARM: tegra: clock: Add Tegra3 0.95V core voltage stepAlex Frid
- Expanded Tegra3 DVFS tables with 0.95V core voltage step - Updated cbus minimum rate calculation, since cbus can not run at 0.95V - Updated PLLM dvfs initialization, since PLLM can no longer be voltage independent, even when its usage is restricted. Bug 817679 Bug 841336 Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4 Reviewed-on: http://git-master/r/74141 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/76463 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limitsAlex Frid
Added alternative frequency limits for Tegra3 CPU. These limits are applied only in the lowest CPU EDP temperature zone, and the offset from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling voltage steps. Offset values as well as temperature threshold are to be updated per characterization. Bug 913884 Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/70189 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/75615 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
2012-01-12ARM: tegra: dvfs: Update Tegra3 vdd_core floorAlex Frid
To properly account for voltage steps with 12.5mV resolution, moved up by 25mV all thresholds in vdd_core floor calculation function, and replaced "less than or equal" comparison with "less than". Change-Id: I869ecabf4e25a268fbe279e54026d4fd1bf25db6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/73903 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-on: http://git-master/r/74558 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
2012-01-06ARM: tegra: dvfs: Update Tegra3 CPU DVFS tablesAlex Frid
Bug 817679 Bug 841336 Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/71755 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-01-06ARM: tegra: dvfs: Re-arrange Tegra3 scaling voltagesAlex Frid
Removed 925mV and 950mV steps / added 1.175mV and 1.212mV Tegra3 CPU voltage scaling steps. Bug 841336 Change-Id: I51f91df857ab3df7d66fcee4cda21318cd3b23eb Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/71738 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
2011-12-21ARM: tegra3: dvfs: Added DVFS entriesMohit Kataria
Added dvfs entries for automotive skus Bug 883565, 882186 Change-Id: I6186b682fa82e24c3062bcbf5c2e5580fdf80562 Signed-off-by: Mohit Kataria<mkataria@nvidia.com> Reviewed-on: http://git-master/r/70292 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2011-11-30ARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltageAlex Frid
Updated Tegra3 xL core speedo and nominal voltage settings. Re-factored nominal voltage selection, since new data introduced dependency of core voltage on both CPU and core speedo id. Bug 841336 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675) (cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301) Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1 Reviewed-on: http://git-master/r/67014 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rd35cb9ac1fbcb424548e05d10d5622744394e796
2011-11-30ARM: tegra: dvfs: Add Tegra3 xL CPU DVFS tablesAlex Frid
Bug 841336 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit d98da0dcb175787a6c6a26c87b6f5ad84ab3da8b) (cherry picked from commit 865746e6c5938db1d7517eca916033ee13e2d290) Change-Id: Ie26a1ccafcf8455a9d4d93d0d4e2fc330f5162f6 Reviewed-on: http://git-master/r/66514 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R8a5f24043e5fdd79cc927ef55f3ea031f093124f
2011-11-30ARM: tegra: dvfs: Update Tegra3 x3 CPU DVFS tablesAlex Frid
Bug 841336 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 459a539b413bc34fa6bed54cc363b4a6ffbaff59) (cherry picked from commit 470c3c4fad40a570dedfd51a52577fd4c91c5269) Change-Id: I63214eaa437345bf7657f4c53a6dd73473e1e532 Reviewed-on: http://git-master/r/66513 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R9e3e92e6c27da3c8760b01cda223463c75d6d16f
2011-11-30ARM: tegra: clock: Support restricted PLLM usageAlex Frid
Added configuration option TEGRA_PLLM_RESTRICTED - when enabled, PLLM - memory PLL - usage may be restricted to modules with dividers capable of dividing maximum PLLM frequency at minimum voltage. When disabled, PLLM is available as a clock source with no restrictions (current configuration), which may effectively increase lower limit for core voltage if high grade SDRAM is used. Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but keep them disabled by default. Bug 884419 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61) (cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3) Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa Reviewed-on: http://git-master/r/66512 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R22de0f09e7af2640499ec8cd96e974328d78bace
2011-11-30ARM: tegra: dvfs: Update Tegra3 EMC DVFSAlex Frid
- Moved validation of EMC maximum rate against nominal core voltage from common dvfs initialization to board specific EMC scaling table setup (a logical place to do it, since EMC DVFS is board dependent) - Used current rate as rounded EMC rate if no EMC scaling table is provided (instead of maximum EMC rate - no sense in attempt to set maximum rate, or any rate, for that matter, if there is no table). - Cleaned EMC initialization procedure (cherry picked from commit 4f655077e09c0dc4abc50d190d82c91473e2e81c) Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit a213668b4f54b8ea7603a6d1e71f8b4ab1998bf7) Change-Id: Id61f33e42556a6415e45b014bcadace600dd86d5 Reviewed-on: http://git-master/r/64765 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R697e04b6140eb0084bdb341febe3acdf91d93535
2011-11-30ARM: tegra: dvfs: Add Tegra3 AP33 dvfs tablesAlex Frid
Bug 841336 (cherry picked from commit b4cd14d5b9d1b2011a7752b6c52b3b64eb227cdb) (cherry picked from commit 24cefb5d699db0a53b9fb3dd7cbe41de93c44e8e) Change-Id: I080b04577697f31d9f9d4e96213630a28844a7db Reviewed-on: http://git-master/r/63358 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R332edca05c942d8698353eb6817ad1acf0a5f8bf
2011-11-30ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP modeAlex Frid
Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero, which could happen only while CPU is in LP mode (and CPU regulator output is turned off by side-band signal, anyway): - Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero - Allow VDD_CPU one step change to zero (i.e., to minimum voltage set by constraints) after entry to LP mode - Allow VDD_CPU one step change to the predicted G mode target before exit from LP mode (cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872) (cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827) Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1 Reviewed-on: http://git-master/r/63357 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94
2011-11-30ARM: tegra: dvfs: Enable EMC bridge if rail is disabledAlex Frid
When core rail is disabled it is set to nominal voltage underneath clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe at high voltage that exceeds EMC bridge minimum level. Enable EMC bridge explicitly in this case to set safe floor for EMC. Similarly need to enable EMC bridge when CPU rail is disabled and pushing core voltage (cpu-to-core voltage dependency) over bridge minimum level. (cherry picked from commit bff814b2e46e67defde178b72bd379003b5429c2) (cherry picked from commit e5567cb8dafcbd30797237e7bb91d77ce57de66a) Change-Id: Ibb8dad5132f69e3325d793658b3dcc8b887974bf Reviewed-on: http://git-master/r/62031 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R56f360c3b1ee25bf2dae4b886399b83e357f0225
2011-11-30ARM: tegra: dvfs: Update cpu nominal voltage selectionAlex Frid
Update cpu nominal voltage selection to accommodate irregular voltage steps in cpu dvfs table (instead of constant 25mV step assumed so far). (cherry picked from commit 3bdc83bebf4ef74c760d075a8ae8ffe6baf8b15a) (cherry picked from commit e2301c1d8e868d4658f768cfacc631c0f78c185b) Change-Id: Ief9298608dd524d7cc7ff4057fc1cffc180e7c82 Reviewed-on: http://git-master/r/62028 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R91e4948134b5b385dff77c6b8f610ab80cf91c6a
2011-11-30ARM: tegra: dvfs: Re-arrange Tegra3 CPU DVFS stepsAlex Frid
Removed 750mV and 775mV steps from Tegra3 CPU voltage ladder (way below VDD_CPU min 850mV), and added 1200mV step needed for future AP33 DVFS support. Bug 841336 (cherry picked from commit 67191a68a25b32299520673e8cdfa4e166c152d0) (cherry picked from commit 7e3cf6cc679afe6828cba64b3e1482585301841a) Change-Id: I3ca97126662204cb0f65ec808609c8135408d7ed Reviewed-on: http://git-master/r/62026 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R321ee8f89da66d2178f98cf4f86e83c9dcc3191b
2011-11-30ARM: tegra: dvfs: Add dvfs table for Tegra3 x3 chipsAlex Frid
Bug 841336 (cherry picked from commit fc2f899fe93cb4aea2e22c18d98b1b856429d572) (cherry picked from commit 252d4bed817eec321dcefe9ba07c6f019b92f8f2) Change-Id: I9522b1289dcd80c23ae47a6015521a85a3b954cc Reviewed-on: http://git-master/r/61710 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7ae4227a1a00ef79aa65018cb771b40c410050e3
2011-11-30ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1VAlex Frid
Change VDD_CPU and VDD_CORE dependencies so that VDD_CORE min is 1.1V when G CPU is active. (cherry picked from commit afdc5d559ef9630e412368492f85332d35468eca) (cherry picked from commit 97c6508452b0e0f40179e8c62d84737839dc9ac2) Change-Id: Ie038ac213c6a0cb817bb506fc3b925ab5e81c156 Reviewed-on: http://git-master/r/61708 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R4d9c5da8191468b56c16dae9f920194186454833
2011-11-30ARM: tegra: dvfs: Add Tegra3 dvfs core cap interfaceAlex Frid
Added Tegra3 kernel dvfs throttling interface for VDD_CORE domains. Requests from this interface are combined with sysfs capping requests and the most aggressive (minimal) cap level is set. (cherry picked from commit da2fa3965fb89ec7faeb49c7b9009bdd949f8fb7) (cherry picked from commit 2b8b7d8d6feba48dde56c7fa3e92f57a9b26e75a) Change-Id: Iadcb8cac04f0793fc2fdc8d8203d3bc973004a1d Reviewed-on: http://git-master/r/61023 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rc4cfbf50089133bd111c1a156d7a77586c6181c2
2011-11-30arm: tegra3: Enable CORE and CPU DVFSGaurav Sarode
Change-Id: I2ceb5ea62c4f8bcc4b4bafc5f842cc2407d172f4 Reviewed-on: http://git-master/r/49831 Tested-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R58663a817de5900221291ff8aef5f199223549e3
2011-11-30ARM: tegra: dvfs: Update Tegra3 CPU dvfs tablesAlex Frid
Bug 817679 Original-Change-Id: I530b96ba23672f27c0d07084d3d881067ae6420f Reviewed-on: http://git-master/r/48823 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R68b819fdd8ad17f9e44276274f5ef66c1419ff50
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-27 22:05:46 +0000