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path: root/arch/arm/mach-tegra/tegra3_emc.c
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2012-08-24ARM:tegra:emc: scale latency allowance by tick lenRay Poudrier
Calculate the tick length of the EMC DFS table and scale the latency allowance settings. Bug 955082 Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/124980 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-20ARM: tegra: clock: relax memory efficiency if 3d clock is offPeter Zu
Bug 1003509 Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206 Signed-off-by: Peter Zu <pzu@nvidia.com> (cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30) Reviewed-on: http://git-master/r/115468 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-13ARM: tegra: clock: Dynamically re-lock memory pllAlex Frid
So far Tegra3 EMC DFS allowed only scaling rates that can be divided down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM is always running at maximum SDRAM rate set at boot time, while PLLP rate 408MHz is fixed across all Tegra3 platforms. This commit implements dynamic re-locking of PLLM at run time. Now memory pll can lock either at boot rate or additional auxiliary rate that is selected as follows: auxiliary PLLM rate must be present in EMC DFS table, it must exactly match one of the rate steps for Tegra3 graphics bus with PLLC clock source (cbus), and must not be a proper factor of boot PLLM rate or PLLP fixed rate. When switching PLLM between boot and auxiliary rate, PLLC is used as backup memory pll, and during this time cbus is locked at auxiliary rate. In addition system bus is forced to temporarily use PLLP as a clock source (this is necessary as sbus main clock source is PLLM secondary divider PLLM_OUT1). Limitations: - only one auxiliary rate is supported, and it should be below PLLM boot rate, but above half of boot rate - dynamic re-lock is allowed only on LPDDR2 platforms - no clock other than EMC and system bus could use PLLM as a source; so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be selected, and VI clock (not covered by PLLM restricted configuration) must be moved to PLLP. Bug 1005576 Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/111438 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a) Reviewed-on: http://git-master/r/114760 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record EMC clock source rateAlex Frid
On Tegra3 added source rate to EMC clock source selection structure, and re-factored EMC DVFS initialization accordingly. Bug 1005576 Change-Id: I155e982bef2431a76cf5e5085070d4e654a7b49b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110935 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bf52c26c532a9ebabc4fc8a1fb5fc9d88be85e66) Reviewed-on: http://git-master/r/114758 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-01ARM: tegra: emc: add reference counting to early ack disablementSang-Hun Lee
Bug 995950 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/110190 (cherry picked from commit cbfc31fb126cd651157125d1785135eced6587dd) Change-Id: I44eb889235db82b0efda238b87be5612425afb9d Reviewed-on: http://git-master/r/110978 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-06-27ARM: tegra: clock: Add fence read in emc clock changeAlex Frid
Added fence read in Tegra3 emc clock change procedure. Change-Id: I2162affb4dddcacf38057e07ff6fbd5964643188 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/106956 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-12emc: tegra3: Change debug eack_state permissionsHao Tang
Remove write permission of eack_state for cts verification. The init script will make it acessible on engineering builds Bug 906796 Change-Id: I1b5d77f4ee3d0e39106840eca0c53e6347c34ea1 Signed-off-by: Hao Tang <htang@nvidia.com> Reviewed-on: http://git-master/r/106668 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-05-21ARM: tegra: clock: Account for memory BW efficiencyAlex Frid
Account for memory efficiency when processing requests from Tegra3 EMC shared bandwidth users. Do not round requests from these users until they are aggregated. The respective debugfs node: /d/tegra_emc/efficiency (in %). Bug 952739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084) Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458 Reviewed-on: http://git-master/r/103499 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-05-17ARM: tegra: emc: add eack_disable functionalityRay Poudrier
Bug 946110 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: I0d4c716c4ab7a60011018d6c13be4265cc9f7290 Reviewed-on: http://git-master/r/87061 (cherry picked from commit a7dad880dcea36fcb8223cf0b34cc1091d725a9f) Reviewed-on: http://git-master/r/102360 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-04-06ARM: tegra: emc: Reduce DDR3 min rate to 25.5MHzDaniel Solomon
Reduce DDR3 min rate to 25.5MHz to save power. Bug 947228 Signed-off-by: Daniel Solomon <daniels@nvidia.com> (cherry picked from commit f09e23ac983a24d9ba03a11764b871b9d548f4dc) Change-Id: I4cd19099943cfa06d7fe7cca308042c44e708748 Reviewed-on: http://git-master/r/93958 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
2012-03-13ARM: tegra: clock: Add SoC-to-DDR bit swap supportAlex Frid
Since Tegra3 allows bit swapping when routing SoC-to-DDR data bus, added the respective decoding mechanism for reading LPDDR2 mode registers. Populated mapping table for PM269 board. Bug 939626 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5f5329596167681b528c87fd088d60030eee6fdc) Change-Id: I6670110a828df4264b8f7a8c8e6e67611a830033 Reviewed-on: http://git-master/r/89350 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-13ARM: tegra: clock: Add LPDDR2 temperature controlsAlex Frid
Added interfaces for - reading scaled LPDDR2 temperature from MR4 register - controlling refresh rate according LPDDR2 specification For now, these interfaces are only used by debufs nodes: /sys/kernel/debug/tegra_emc/dram_temperature (read only) /sys/kernel/debug/tegra_emc/over_temp_state (read/write, 0 - set regular low temperature refresh rate, 1 - speed up refresh for high temperature) Bug 939626 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 373ff7e49235f6e222b42e324b6a2dc9eac633e6) Change-Id: I9cfaaeeab16d5b49acb91824fecc6b0ee8f3cdbb Reviewed-on: http://git-master/r/89349 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-13ARM: tegra: clock: Update Tegra3 EMC timing trackingAlex Frid
Separated tracking of Tegra3 EMC timing settings from EMC rate statistic, as the same rate may be configured with different timing (e.g., BCT timing and DVFS timing are not the same even for the same rate). Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit cbf5634f67d3fb53ad01bb632905cf311052e2f1) Change-Id: I4015d31297e9be29ec2d3f298ad33bc59bf45836 Reviewed-on: http://git-master/r/89348 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-03-13ARM: tegra: clock: Disable early-ack during EMC clock changeAlex Frid
Bug 935079 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit edf6b3ed22c4f803bf13d1bf6316ffb01c8946dc) Change-Id: Ifd155a66469e9463da89639b6577c1f90972f4ac Reviewed-on: http://git-master/r/89347 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-11-30ARM: tegra: dvfs: Make EMC voltage scaling board dependentAlex Frid
Added minimum voltage field to Tegra3 EMC frequency scaling table. Adjusted default (common) EMC DVFS mapping, respectively, when EMC frequency table for the particular board/dram chip combination is loaded. Bug 895245 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 1fe4d12c4abdd08abd45eb755d3d50780cafb19c) (cherry picked from commit 4020c6aacfd5ec3c7106cc05e720bc4c356ac58d) Change-Id: Ia10183001996aee37259efdb533640ebf72d552a Reviewed-on: http://git-master/r/67012 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rb1cb3a849c9c870b0c338a5a0a7e9cb9a7572674
2011-11-30ARM: tegra: clock: Update EMC clock change procedureAlex Frid
Set MC arbiter limits before EMC clock change on Tegra3. Bug 896654 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 16f545012457a04ba38f4f8bf80646b18a74cb2f) (cherry picked from commit bd29cb18f1d26cc3a0fdc8933a08158d623fed58) Change-Id: I080f21030007909bece5272ccdb93f8a85d4b13b Reviewed-on: http://git-master/r/66515 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R0561570b37cdff800f0a7f71558eef16eb82cc59
2011-11-30ARM: tegra: dvfs: Update Tegra3 EMC DVFSAlex Frid
- Moved validation of EMC maximum rate against nominal core voltage from common dvfs initialization to board specific EMC scaling table setup (a logical place to do it, since EMC DVFS is board dependent) - Used current rate as rounded EMC rate if no EMC scaling table is provided (instead of maximum EMC rate - no sense in attempt to set maximum rate, or any rate, for that matter, if there is no table). - Cleaned EMC initialization procedure (cherry picked from commit 4f655077e09c0dc4abc50d190d82c91473e2e81c) Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit a213668b4f54b8ea7603a6d1e71f8b4ab1998bf7) Change-Id: Id61f33e42556a6415e45b014bcadace600dd86d5 Reviewed-on: http://git-master/r/64765 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R697e04b6140eb0084bdb341febe3acdf91d93535
2011-11-30ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS tableAlex Frid
Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This field will be supported starting with table revision to 3.2, and it will allow to enable/disable DSR for each table entry independently. Bug 853990 (cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac) (cherry picked from commit c7ebe73da695206a992088a4ba5a6cd7643ea333) Change-Id: I212d5992067baffaaf5b2e1de25b103c7b1fb56a Reviewed-on: http://git-master/r/63356 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R7261d49b023634a783ab2bd55f494112d0bac2a1
2011-11-30ARM: tegra: power: Enable Tegra3 EMC bridge in suspendAlex Frid
When dvfs is suspended core rail is set to nominal voltage underneath clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe at high voltage that exceeds EMC bridge minimum level. Enabling EMC bridge during suspend for Tegra3 DDR3 platforms guarantees safe EMC operations at high voltage. (cherry picked from commit 677c01d3d9edaf7e91f09de5025e7864b6a288d8) (cherry picked from commit 75710c173caa46f2e3cd24e48cc82f030cdb52d9) Change-Id: I1e300c18867295b1394184da39eeffcab43de4c7 Reviewed-on: http://git-master/r/62030 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R2a3a91b370d2517e89e1d30f27f9fd41a9a81267
2011-11-30ARM: tegra: clock: Update Tegra3 EMC clock configurationAlex Frid
- Moved initialization of Tegra3 dram configuration variables from EMC DVFS setup to EMC clock initialization, so that these variables can be used independently of DVFS. - Added graceful exit from EMC DVFS setup in case of empty DVFS table - Applied EMC minimum rate to direct EMC clock round rate operations (currently applied only to shared EMC bus update). (cherry picked from commit c6b3f6e0eb0b6e3485d02fc5306a1c09cbacf914) (cherry picked from commit cbf09d55bb9fa9c9ade7bb472859b4808f47b615) Change-Id: I84bbdc05ff7a0670ec9d088b98a9df25683db4df Reviewed-on: http://git-master/r/62029 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0fb03ff9903aa51aa922b4a49eed96aad0e97a06
2011-11-30video: tegra: dc: fix tiled memory efficiencyXin Xie
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3. This patch adds one memory controller API to retrive tiled memory efficiency. BUG 847731 Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1 Reviewed-on: http://git-master/r/40074 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R5675398d3066d01d3d46f26267eddbba1accc815
2011-11-30ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHzAlex Frid
Original-Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b Reviewed-on: http://git-master/r/41141 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R47886089e5b3b73c58372645ec7ea282a0cfa698
2011-11-30ARM: tegra: clock: Clean tegra3_emc.c macro styleAlex Frid
Original-Change-Id: I472be800ad84b79783577264b51c6478aa4bb41b Reviewed-on: http://git-master/r/40769 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R0b3b4124618ecafc6f83ff165634ebba664a24a1
2011-11-30ARM: tegra: clock: Support Tegra3 EMC DFS table revisionAlex Frid
Support Tegra3 EMC DFS table revision 3.1 that includes two additional EMC shadow registers (reserved with previous table revision 3.0). Bug 836260 Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb Reviewed-on: http://git-master/r/40749 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478
2011-11-30ARM: tegra: clock: Fix Tegra3 EMC clock change procedureAlex Frid
Fixed EMC clock change procedure to skip XM2CLKPADCTRL register during shadow burst write, and set it within unshadowed section. Bug 836260 Original-Change-Id: Ief92c7d3957c9685b8c528297da2e905159a530d Reviewed-on: http://git-master/r/40748 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R5016ffd224db2b3eb6639a6b33063d1c27456b24
2011-11-30ARM: tegra: clock: Add Tegra3 emc high voltage bridgeAlex Frid
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz can not work at high core voltage; the intermediate step (bridge) is mandatory when core voltage is crossing the 1.2V threshold (fixed for Tegra3 arch). In addition emc must run above bridge rate if any other than emc clock requires high voltage. EMC bridge is implemented as a special emc shared user: its rate is set once during emc dvfs table initialization; then, the bridge is enabled or disabled when sbus and/or cbus voltage requirement is crossing the threshold (sbus and cbus together include all clocks that may require voltage above threshold - other peripherals can reach their maximum rates below threshold). Bug 846693 Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf Reviewed-on: http://git-master/r/39919 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
2011-11-30ARM: tegra: power: Restore Tegra3 EMC power setting after deep sleepAlex Frid
Bug 836334 Original-Change-Id: I19587e97af0addc62217466ee977c5afc33a6028 Reviewed-on: http://git-master/r/39854 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R2748dbb3f7308ae491e137062e2b0f940fb8185e
2011-11-30ARM: tegra: dvfs: Update Tegra3 EMC DFSAlex Frid
Updated Tegra3 EMC clock change procedure with periodic qrst support, and EMC DFS tables. Bug 836260 Change-Id: Ia3d7f58bf61ee6e695ab62f934388d4c1b4d2079 Reviewed-on: http://git-master/r/35321 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Rc4b52e82783d355ec3a600d636b0871119a200d5
2011-11-30ARM: tegra: power: Re-initialize Tegra3 EMC after LP0Alex Frid
Since EMC frequency is not restored after exit from LP0, re-initialize EMC clock with the new warm boot configuration, and make sure that the 1st after LP0 clock change does not use stale timing cache. Skip Tegra2 specific EMC restoration on Tegra3 platforms. Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2 Reviewed-on: http://git-master/r/26807 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406 Rebase-Id: Rb3fcd60c0c674e10d41d4cdc4d8e53a6e124a5bf
2011-11-30ARM: tegra: clock: Modify EMC maximum rate settingsAlex Frid
On A01 Tegra3 chip EMC rate may not reach full PLLM range - set maximum EMC rate equal to boot rate. Use PLLM frequency as EMC rate limit for A02+ chips. Original-Change-Id: I0b901a29d628362b09f2a3d0ce908b4019804cfd Reviewed-on: http://git-master/r/26786 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I741fcfca646ba0a2a8732dbccaf7a2642d839809 Rebase-Id: R9b5913cccecc96221c1541887e6e3b03a8f1316a
2011-11-30ARM: tegra: clock: Updated EMC clock change procedureAlex Frid
Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f Reviewed-on: http://git-master/r/25177 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8 Rebase-Id: R6416c2a2c2c1dc1fd8619842b91fea24ae10b675
2011-11-30ARM: tegra: dvfs: Add emc dfs statisticAlex Frid
Original-Change-Id: I191ce07b461c9283d61000ca81746b282502f786 Reviewed-on: http://git-master/r/22530 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I81d6caa3c8f6a0c267d171f38156657ef8c52688 Rebase-Id: R9d9ce785a3e65a0851b3f70159395ed6753bdf87
2011-11-30ARM: tegra: dvfs: Add Tegra3 EMC scaling mechanismAlex Frid
Original-Change-Id: I23954a8d005fae93866666fff0e56edb23a49d46 Reviewed-on: http://git-master/r/21940 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I31c3910d38f9999ddbf3414e042e1972d9a86c5a Rebase-Id: Rd6ca05872b34fa23bef682b4185fb4f354632c3a
2011-11-30ARM: tegra: clock: Add Tegra3 EMC shared busAlex Frid
Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94 Reviewed-on: http://git-master/r/15349 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777 Rebase-Id: R3cab0fa7760e2c6eb5d6e84bbc3dca8f6fe3d3fa
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