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path: root/arch/arm/mach-tegra/tegra3_emc.h
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2014-03-13platform: tegra: emc: Move EMC headerAlex Waterman
Move the core EMC header to a common location. This allows different sources to include it without the annoying "../../" type stuff. Change-Id: I57d2d35e1961eca23d7dd69c2634e8e9af52d4b1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/376787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
2013-09-14ARM: tegra: clock: Add common EMC interface headerAlex Frid
Change-Id: I78538ad9a0061ba09bad5fb122ff672c93caef88 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/192625 (cherry picked from commit 558a32fde1dce6f34d379da0f33477b5992c1963) Reviewed-on: http://git-master/r/194928 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14arm: tegra: mc: set extra snap value for VIKrishna Reddy
This is necessary to avoid VI starving out during high bandwidth use cases. Bug 1059264 Change-Id: I4ed43f13b5a9907d98ae2ddf842a66b5dc8384d6 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/142076 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shiva Dubey <sdubey@nvidia.com> Reviewed-by: Zhaoyi Wei <zwei@nvidia.com> Rebase-Id: R4af947cb9962a159dccbc6ef588fb11d8f51a0f5
2013-09-14ARM: tegra: Add DT support for Tegra30 EMC tablesPrashant Gaikwad
Implements function to parse EMC tables from device tree. Bug 999688 Change-Id: I9c5b028feed46dc8b720220d97e360a3c7ced603 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/130699 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Rebase-Id: R2c3620ae73523a2849ce8ec89387c69fae81370f
2013-09-14ARM:tegra:emc: scale latency allowance by tick lenRay Poudrier
Calculate the tick length of the EMC DFS table and scale the latency allowance settings. Bug 955082 Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Reviewed-on: http://git-master/r/124980 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: Rf0641996f72b0e36d072a6cd935d0452902329b5
2013-09-14ARM: tegra: clock: relax memory efficiency if 3d clock is offPeter Zu
Bug 1003509 Change-Id: I8fb2c0cff7106671f8470b836ea26c09350d6206 Signed-off-by: Peter Zu <pzu@nvidia.com> (cherry picked from commit df2dda0438c2aed3a961d197dce7319fefdf5b30) Reviewed-on: http://git-master/r/115468 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Re47cc8ee4befcb1e22bdcf04db65d85d9736a820
2013-09-14ARM: tegra: emc: add reference counting to early ack disablementSang-Hun Lee
Bug 995950 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/110190 (cherry picked from commit cbfc31fb126cd651157125d1785135eced6587dd) Change-Id: I44eb889235db82b0efda238b87be5612425afb9d Reviewed-on: http://git-master/r/110978 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R2dc2c8b97e7fd3448402c2536a765ff9c86c9181
2013-09-14unknown changes from android-tegra-nv-3.4Dan Willemsen
Rebase-Id: R940fad74c7e91ef3d1d3d589a48064ccb7335541
2013-09-14fixup: continue passing clk to tegra3_emcDan Willemsen
Rebase-Id: R1ee8010170ffe1014ab878a024baf90b10ef2ef3
2013-09-14fixup: emc: move clk_min to pdevDan Willemsen
Rebase-Id: R83b293e052f09fce49cd499e555d1347d72687d4
2013-09-14ARM: tegra: clock: Account for memory BW efficiencyDan Willemsen
Account for memory efficiency when processing requests from Tegra3 EMC shared bandwidth users. Do not round requests from these users until they are aggregated. The respective debugfs node: /d/tegra_emc/efficiency (in %). Bug 952739 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 86929087f68c4366d6179101eb9a6a6473a4f084) Change-Id: I4acdd89f44de1401ce5dad8fc4936932df014458 Reviewed-on: http://git-master/r/103499 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit Rebase-Id: R2eb7759cf7b9fa81bdc1fb7d5d5fba1a58eac25e
2013-09-14ARM: tegra: emc: add eack_disable functionalityRay Poudrier
Bug 946110 Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com> Change-Id: I0d4c716c4ab7a60011018d6c13be4265cc9f7290 Reviewed-on: http://git-master/r/87061 (cherry picked from commit a7dad880dcea36fcb8223cf0b34cc1091d725a9f) Reviewed-on: http://git-master/r/102360 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R2a3875bc982b2e6218188f3bf9259c37d2913b54
2013-09-14ARM: tegra: clock: Add SoC-to-DDR bit swap supportAlex Frid
Since Tegra3 allows bit swapping when routing SoC-to-DDR data bus, added the respective decoding mechanism for reading LPDDR2 mode registers. Populated mapping table for PM269 board. Bug 939626 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5f5329596167681b528c87fd088d60030eee6fdc) Change-Id: I6670110a828df4264b8f7a8c8e6e67611a830033 Reviewed-on: http://git-master/r/89350 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Ra7f7bcb762eb542812e42a2b7d748a78429bf4b5
2013-09-14ARM: tegra: clock: Add LPDDR2 temperature controlsAlex Frid
Added interfaces for - reading scaled LPDDR2 temperature from MR4 register - controlling refresh rate according LPDDR2 specification For now, these interfaces are only used by debufs nodes: /sys/kernel/debug/tegra_emc/dram_temperature (read only) /sys/kernel/debug/tegra_emc/over_temp_state (read/write, 0 - set regular low temperature refresh rate, 1 - speed up refresh for high temperature) Bug 939626 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 373ff7e49235f6e222b42e324b6a2dc9eac633e6) Change-Id: I9cfaaeeab16d5b49acb91824fecc6b0ee8f3cdbb Reviewed-on: http://git-master/r/89349 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rf59ca31cf6bf91172c3f536273ded55bac28db31
2013-09-14ARM: tegra: clock: Disable early-ack during EMC clock changeAlex Frid
Bug 935079 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit edf6b3ed22c4f803bf13d1bf6316ffb01c8946dc) Change-Id: Ifd155a66469e9463da89639b6577c1f90972f4ac Reviewed-on: http://git-master/r/89347 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rcf99ed43cf52be47c64648f1b94358572e5243d7
2013-09-14ARM: tegra: clock: Update EMC clock change procedureAlex Frid
Set MC arbiter limits before EMC clock change on Tegra3. Bug 896654 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 16f545012457a04ba38f4f8bf80646b18a74cb2f) (cherry picked from commit bd29cb18f1d26cc3a0fdc8933a08158d623fed58) Change-Id: I080f21030007909bece5272ccdb93f8a85d4b13b Reviewed-on: http://git-master/r/66515 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R0561570b37cdff800f0a7f71558eef16eb82cc59
2013-09-14ARM: tegra: clock: Update Tegra3 EMC clock configurationAlex Frid
- Moved initialization of Tegra3 dram configuration variables from EMC DVFS setup to EMC clock initialization, so that these variables can be used independently of DVFS. - Added graceful exit from EMC DVFS setup in case of empty DVFS table - Applied EMC minimum rate to direct EMC clock round rate operations (currently applied only to shared EMC bus update). (cherry picked from commit c6b3f6e0eb0b6e3485d02fc5306a1c09cbacf914) (cherry picked from commit cbf09d55bb9fa9c9ade7bb472859b4808f47b615) Change-Id: I84bbdc05ff7a0670ec9d088b98a9df25683db4df Reviewed-on: http://git-master/r/62029 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R0fb03ff9903aa51aa922b4a49eed96aad0e97a06
2013-09-14ARM: tegra: power: Restore Tegra3 MC registers after LP0Alex Frid
On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers that are not saved in PMC scratch file for boot-rom restoration. Since SDRAM after LP0 is running at boot rate, MC registers are saved only once during initialization. Bug 874351 (ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d) Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678 Reviewed-on: http://git-master/r/61045 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301
2013-09-14video: tegra: dc: fix tiled memory efficiencyXin Xie
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3. This patch adds one memory controller API to retrive tiled memory efficiency. BUG 847731 Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1 Reviewed-on: http://git-master/r/40074 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rb0846a0b29dc838a3bb1e76c3a59da0bfc5bbf12
2013-09-14ARM: tegra: clock: Support Tegra3 EMC DFS table revisionAlex Frid
Support Tegra3 EMC DFS table revision 3.1 that includes two additional EMC shadow registers (reserved with previous table revision 3.0). Bug 836260 Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb Reviewed-on: http://git-master/r/40749 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478
2013-09-14ARM: tegra: clock: Add Tegra3 emc high voltage bridgeAlex Frid
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz can not work at high core voltage; the intermediate step (bridge) is mandatory when core voltage is crossing the 1.2V threshold (fixed for Tegra3 arch). In addition emc must run above bridge rate if any other than emc clock requires high voltage. EMC bridge is implemented as a special emc shared user: its rate is set once during emc dvfs table initialization; then, the bridge is enabled or disabled when sbus and/or cbus voltage requirement is crossing the threshold (sbus and cbus together include all clocks that may require voltage above threshold - other peripherals can reach their maximum rates below threshold). Bug 846693 Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf Reviewed-on: http://git-master/r/39919 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff
2013-09-14ARM: tegra: power: Restore Tegra3 EMC power setting after deep sleepAlex Frid
Bug 836334 Original-Change-Id: I19587e97af0addc62217466ee977c5afc33a6028 Reviewed-on: http://git-master/r/39854 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R2748dbb3f7308ae491e137062e2b0f940fb8185e
2013-09-14ARM: tegra: clock: Updated EMC clock change procedureAlex Frid
Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f Reviewed-on: http://git-master/r/25177 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8 Rebase-Id: R6416c2a2c2c1dc1fd8619842b91fea24ae10b675
2013-09-14arm: tegra: Enable MC early ACK and scoreboardScott Williams
Bug 791803 Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432 Reviewed-on: http://git-master/r/23584 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2 Rebase-Id: R3308cf0a852ee2bf0e2adb3de17cebc81e48c71c
2013-09-14ARM: tegra: dvfs: Add Tegra3 EMC scaling mechanismAlex Frid
Original-Change-Id: I23954a8d005fae93866666fff0e56edb23a49d46 Reviewed-on: http://git-master/r/21940 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I31c3910d38f9999ddbf3414e042e1972d9a86c5a Rebase-Id: Rd6ca05872b34fa23bef682b4185fb4f354632c3a
2013-09-14ARM: tegra: clock: Add Tegra3 EMC shared busAlex Frid
Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94 Reviewed-on: http://git-master/r/15349 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777 Rebase-Id: R3cab0fa7760e2c6eb5d6e84bbc3dca8f6fe3d3fa
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