| Age | Commit message (Expand) | Author |
|---|---|---|
| 2013-07-26 | ARM: tegra: clock: Re-factor core bus limit structures | Alex Frid |
| 2013-07-23 | ARM: tegra: clock: Add sysfs interface for bus floors | Alex Frid |
| 2013-07-22 | ARM: tegra: dvfs: Decouple nominal and detached voltages | Alex Frid |
| 2013-05-14 | ARM: tegra: power: Re-factor core voltage capping | Alex Frid |
| 2013-02-08 | ARM: tegra: clock: Moved common bus capping code | Alex Frid |
| 2013-01-27 | ARM: tegra: dvfs: Move common core voltage capping code | Alex Frid |
 |
index : linux-toradex.git | |
| Linux kernel for Apalis, Colibri and Verdin modules | Marcel Ziswiler |
| summaryrefslogtreecommitdiff |