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path: root/arch/arm/mach-tegra/timer-t3.c
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2012-07-19ARM: tegra: Fix build issue for no-SMPAlex Waterman
Fix issues causing the kernel build to fail with CONFIG_SMP not set. Change-Id: I8c7a49970e55354e38ce41d2d1e0dab00ba78f24 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/114317 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-06-14ARM: tegra: resolve compilation time warningsSanjay Singh Rawat
- Adding flag to treat warning as error. - Handling warnings of unused variable, structures and functions, wrong return type, wrong type comparision. Bug 949219 Change-Id: I9d02387ce1073c4e46f69d01669285aa3754f1d9 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/104968 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2012-03-05ARM: tegra: power: Fix LP2 timers suspend/resumeAlex Frid
On entry/exit to suspend state remove/restore Tegra3 LP2 wake timers interrupts affinity to the respective secondary CPUs. Change-Id: I9b46c5fa446a8c6e813343f4564abda5313853da Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/87541 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-02-23ARM: tegra: power: Power off multiple CPUs on-lineAlex Frid
Currently on Tegra3 cpu complex is powered off in idle (enters CPU0 LP2 state) only if all secondary CPUs are off-line. This commit adds an option for CPU0 to enter LP2 while secondary CPUs are still on-line but have been power gated and entered LP2 state by themselves. The critical race: secondary CPU is waking up from LP2, while CPU0 is turning common CPU rail off, is addressed as follows. 1. When entering LP2 state on CPU0: a) disable GIC distributor b) check that CPU1-3 are all power-gated (i.e., either off-lined or have entered LP2) c) if (b) passes - set all interrupts affinity to CPU0, then re-enable distributor and continue with CPU complex powering off d) if (b) fails - re-enable distributor and enter clock-gated (LP3) state on CPU0 This procedure prevents waking secondary CPUs by GIC SPIs. 2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ or private timers would happen. This is achieved by disabling timers and legacy interrupts if CPU1-3 enters LP2 state with external timers selected as wake sources. Respectively, establish dependency between turning rail off and LP2 wake timers configuration options. 3. Finally, no IPIs is sent by CPU0 entering LP2. There are no special changes in wake up procedures - whenever CPU0 is awaken by external interrupt or wake timer, cpu complex is powered on by h/w, and secondary CPUs that were in LP2 state are ungated by the same interrupt (off-line CPUs are kept power gated). Hence, there is no need for CPU1-3 external wake timers to run while the rail is off, and these timers are stopped. To make sure that none of secondary CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep interval of all CPUs. By default configuration option for powering off multiple on-line CPUs is disabled on Tegra3. Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83547 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-02-17ARM: tegra: power: Add external LP2 wake timers on secondary CPUsAlex Frid
Add an option to use external timer as Tegra3 secondary CPU wake source from lp2 (power gated) state. This is a follow up to commit 51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from external timer, since its interrupt is registered too late - after secondary CPU is brought on-line, and already had a chance to enter lp2. With this commit, secondary CPU is not allowed to enter lp2 in idle until wake timer is registered (clock-gated lp3 state is entered instead). External timer wake up mechanism is enabled on Tegra3 only if option HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU timers as lp2 wake sources. Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/83546 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-02-15ARM: tegra: clocks: Consolidate input frequency measurementsScott Williams
Consolidate the functions used to measure the input frequency into a single implementation and perform the measurement only once. Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83613 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2011-11-30arm: tegra: timer: Fix compiler warningScott Williams
Fix compiler warning when PM_SLEEP and HOTPLUG_CPU are not configured. Change-Id: I6e9e7aaf9c63752d0c33363b1cced75b4437d82d Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/66508 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Gerrit_Virtual_Submit Rebase-Id: R5687b9e034e004907ba01263948bf839544adb1b
2011-11-30ARM: tegra: power: Fix non-SMP LP2 timer registration issuesScott Williams
Don't call irq_set_affinity() on non-SMP systems. Change-Id: I728d5163bff3fb2bd4a2ea7946d2e57cb0854589 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49346 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com> Rebase-Id: R470db120396c95bdcafc48ba357652a43d63da82
2011-11-30ARM: tegra: timer: Use common chip id functionsScott Williams
Original-Change-Id: Ibf7a37c0751924f0a8de4932d0d31b6fe6c3c4e8 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/49049 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Rebase-Id: Rfcfb080975c0f844487b91167fc455882f0cb5f4
2011-11-30arm: tegra: Use new platform typesYudong Tan
This change is needed to support three different platforms, silicon, fpga and simulation. Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce Reviewed-on: http://git-master/r/36351 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
2011-11-30ARM: tegra3: Add LP2 TimersScott Williams
Change-Id: I121c8aff9c4cb212ac625ef7751d8cf6b8093068 Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes, move hotplug notifier to timer-t3.c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbfbfdb1720960dd9ce2847fb16daa932bebb16d2
2011-11-30ARM: tegra: Move common timer code into timer.cScott Williams
The system timer initialization code for Tegra2 and Tegra3 is essentially the same except for the actual physical timer used and the range of possible reference clock frequencies. This change removes the needless duplication of code and restructures the system timer code into common and SOC-specific parts. Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15
2011-11-30HACKY: timer-t3 updates for K39Dan Willemsen
Rebase-Id: Re2ca6bafa842d114859a40c7ab19097fd86fc635
2011-11-30arm: tegra: timer: New Tegra3 IRQ mappingScott Williams
Rename timer.c to timer-t2.c for consistency with other chip-specific implementations. Bug 790458 Bug 790448 Bug 738259 Original-Change-Id: I7e0fceb716590cd92b64ba00c0bebe659e9beb21 Reviewed-on: http://git-master/r/22885 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I322324c2177d57657a63e9428f8e49d5df2b828e Rebase-Id: R7312866cdc8044a71cc2f83ad4bc7aa66b07416d
2011-11-30ARM: tegra: timer: Restructure timer controllers usage.vdumpa
Restructure timer controller usage in order to add Lp2 wake timers for all cpu's. Bug 790458 Original-Change-Id: Ie71eb9fb8c1bee0bd059d40b1761718931c9bfe0 Reviewed-on: http://git-master/r/20692 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Original-Change-Id: I16ccea6db75ec4fd0d7da264c37b311113e59fd7 Rebase-Id: Rf0292ae426d874ac8c7cd0fa988ba7314c5256a2
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