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path: root/arch/arm/mach-tegra/timer.h
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2013-02-06ARM: tegra11x: Fix wake-up time adjustmentBo Yan
The wake up time adjustment for per-core CPU power down entry has a few issues: the logic of checking masking bit is wrong and unnecessary, the timer function for getting context is not used elsewhere and seems redundant, the calculating statement itself is confusing. This patch aims to fix issues above. Change-Id: Id717f50005e0c32db80af786d9b1fbbe628c196a Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/197065 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2013-01-28ARM: tegra11x: more accurate sleep timeBo Yan
The sleep length in tick data structure does not reflect how long timer has been running, thus the expected wake up trigger may be set to a value which is too late. Directly accessing timer register to get the next timer event, which is then used to calculate the expected wake up time. This implies we are sleeping shorter than before in case of cluster power down, but will make sure we don't oversleep. Change-Id: I84598db30b6a739103026d090b130f3adb63147b Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/193483 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-11-14ARM: tegra: pm: adding timestamp to suspend traceSivaram Nair
Tegra RTC counter value is added to the suspend trace calls so that wakeup latency can be measured. Change-Id: Ibe97b50d89a843c6caffc02587f398ff5d2936a6 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/162302 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-10-22ARM: tegra11x: Fix TimerValue data typeBo Yan
The TimerValue register in generic timer does not stop after counting to 0, it will keep counting down. The value is the time elapsed after event trigger. Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/139535 (cherry picked from commit f84b23ed0c37297bf8142b69702cf8f2a1c24058) Change-Id: I009585819b801b2eb157f9a70a3e9bf75a41ff77 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/146479 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-08-09ARM: Tegra: remove tegra_get_linear_age() from under CONFIG_HAVE_ARM_TWDVarun Wadekar
Change-Id: Ib106db20f587e53c95410fcc3d834c257b112a19 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-08-06ARM: tegra: dvfs: Adjust VDD_CPU to offset agingAnshul Jain
Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-27ARM: tegra11: Use CPU private timer for LP2Bo Yan
There is no new change for T20 and T30. For SoCs with arch timer support, arch timer is used for LP2 accounting. Also removed ARM_SMP_TWD option from Kconfig, it's no longer necessary and deprecated. Change-Id: I4292e333df97da296318224e0aa1411330f67900 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/118365 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-07-24ARM: tegra11: Save & restore timer registersBo Yan
Save & restore generic timer registers across cluster switch. Change-Id: I8a7e131dede5b21259868edf4fff2df8a20c93c2 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/116859 Reviewed-by: Automatic_Commit_Validation_User
2012-07-03ARM: Tegra: fix arch timer registration sequenceVarun Wadekar
Change-Id: I94d4ab5c8d53e454bbd09b6ef2586b1baf69d456 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/113243 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
2012-06-26ARM: tegra: Rename arch timer suspend/resume functionsScott Williams
The arch timer suspend/resume functions are somewhat misnamed. They are more correctly Timer Stamp Counter (TSC) suspend/resume functions. Rename them accordingly. Change-Id: I81c3c0385b03a6b0d80613528ce8c8e505391f32 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/89814
2012-06-26ARM: tegra: power: Add TSC suspend/resumeScott Williams
Change-Id: Id52c906149f9c7e72501b50ead3912228aea033a Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/84151 Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-06-26ARM: tegra11: clocks: Remove TWD clocksScott Williams
Tegra11x will never have ARM TWDs so remove the clock entries that were propagated from the original Tegra3 tables. Change-Id: Ic6e551271f373e67e6c541f56e0a392e55ba8b27 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83538 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com>
2012-06-26ARM: tegra: clock: Make TWD optionalScott Williams
Do not initialize the TWD clock if HAVE_ARM_TWD is deselected. Also moves all TWD initialization out of the common clock file and into the common timer file. Change-Id: Ie18594c571bd662c495ae4d786b70eb07b8d1437 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/83265 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Mark Stadler <mastadler@nvidia.com>
2012-04-10ARM: tegra: timer: fix timer init sequenceVarun Wadekar
rip out common things from tegra2/3 code and include them in the common timer init sequence. Change-Id: Ia6f3dc26b6ddbbc89640a6831b011d69d233338e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-22ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entryAlex Frid
When Tegra3 secondary CPU is entering LP2, read TWD timer state into context structure, rather than separate local variables. Reviewed-on: http://git-master/r/77957 Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78899 Reviewed-by: Automatic_Commit_Validation_User Rebase-Id: Ra2fb8f72f23c8aac06757aba504623ea45ae4185
2012-03-22ARM: tegra: power: Add TWD context save/restoreScott Williams
Change-Id: I629f77041ce444dfff32b563795573174afea3a1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R7a21e91127b44461d219a8bfd388f99ba7a72b53
2012-03-22ARM: tegra: Move common timer code into timer.cScott Williams
The system timer initialization code for Tegra2 and Tegra3 is essentially the same except for the actual physical timer used and the range of possible reference clock frequencies. This change removes the needless duplication of code and restructures the system timer code into common and SOC-specific parts. Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b Signed-off-by: Scott Williams <scwilliams@nvidia.com> DW: Split into logical changes Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15
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