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2012-10-03tegra: colibri_t30: hack to avoid clock warningsMarcel Ziswiler
Hack to avoid extensive warnings being logged during boot-up due to CPU clock adjustments before regulator being ready.
2012-10-03tegra: colibri_t30: initial Toradex Colibri T30 L4T R16 supportMarcel Ziswiler
Tested on early prototype Colibri T30 V1.0a eMMC module. Known issues: - spurious boot hang after following kernel message [ 5.595219] Timed out waiting for lock bit on pll pll_a - no audio (SGTL5000) support integrated yet - NAND detection/support disabled for now due to boot hang - USB OTG support disabled for now due to boot hang - trying to spawn L4T R16 X driver seems to hang Note: requires uImage with adjusted entry point/load address as follows mkimage -A arm -C none -O linux -T kernel -a 0x82008000 -e 0x82008000 -n 'Linux-3.1.10-colibri_t30' -d zImage uImage
2012-10-03tegra: colibri_t20: clock clean-upMarcel Ziswiler
Clean-up some of the early clock initialisation hacks.
2012-10-02tegra: colibri_t20: add more video modesMarcel Ziswiler
Add the following tested (e.g. framebuffer console and X) video modes: - 800x480@60 (e.g. for EDT ET070080DH6) - 800x600@60 - 1024x768@60 - 1024x768@75 - 1280x720@70 aka 720p - 1366x768@60 The define TEGRA_FB_VGA in board-colibri_t20.h can be used to switch between VGA and 800x480.
2012-10-01tegra: colibri_t20: fix pwm backlightMarcel Ziswiler
Fix PWM backlight by using PWM<A> rather than PWM<C> by default. Invert brightness value due to unified TFT interface displays (e.g. EDT ET070080DH6) inverted LEDCTRL pin behaviour (e.g. 0V brightest vs. 3.3V darkest) and use PWM frequency of 1 kHz as recommended. Add comment about PWM pin muxing. While at it do some ifdef and indentation clean-up.
2012-10-01tegra: fix usb_phy build breakage if gadget as moduleMarcel Ziswiler
Add missing symbol exports to address gcc 4.7.2 from oe-core throwing following errors if usb gadget stuff compiled as modules (cf. 328d61af72a8f59f5dc53db8cddf8c8e572ad958).
2012-09-10tegra: colibri_t20: incorporate l4t-r16 changesMarcel Ziswiler
Incorporate L4T R16 changes from NVIDIA Ventana. Note: USB OTG port not functional as of yet.
2012-09-10Merge branch 'l4t/l4t-r16' into colibriMarcel Ziswiler
Merge with latest NVIDIA L4T R16. Only real conflict concerning inverted VBUS gpio support.
2012-09-10tegra: colibri_t20: USB clean-upMarcel Ziswiler
Re-enable USB Ethernet gadget. Clean-up USB platform data.
2012-09-02tegra: colibri_t20: fix i2c usageMarcel Ziswiler
The I2C2 controller is used for display EDID via DDC_CLOCK/DATA on X3 pin 15/16. The regular GEN2_I2C pins can not be used for I2C functionality on the Colibri T20. The I2C3 controller can optionally be used via CAM/GEN3_I2C on SODIMM pin 127/133.
2012-08-15ARM: tegra: usb: regulator on during lp0 on T20Krishna Yarlagadda
Tegra 2 requires regulator to be on during lp0 Bug 1012273 Bug 1030730 Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-on: http://git-master/r/116743 (cherry picked from commit 50331bba385d880f74dd9dcbce8a32d6f4e49f8c) Change-Id: I8106582529fbb5d6fed76e56b32871af8806b918 Reviewed-on: http://git-master/r/123681 Tested-by: Peer Chen <pchen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-08-07arm: tegra: cardhu: Reserve 16MB on RAM for HDMIShashank Sharma
Reserve 16MB for HDMI maximum possible resolution (1920x1080) at 32 bpp and double buffering. Change-Id: Id719a875b805723758485f970ab9e2f1a28ed19b Signed-off-by: Shashank Sharma <shashanks@nvidia.com> Reviewed-on: http://git-master/r/121562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kiran Adduri <kadduri@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com>
2012-08-07ARM: tegra: usb_phy: prevent illegal access to registersRakesh Bodla
Adding the conditions to prevent illegal register access. Bug 993380 Change-Id: I8e275846612cbac70c1f50251d5f5d0700e845b0 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/117289 (cherry picked from commit c1513eaf68090a268f8ec1b2b6c7e7381c16dfdd) Reviewed-on: http://git-master/r/117996 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Preetham Chandru <pchandru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-08-03ARM: tegra3: clock: Put graphic clks to safe rangeJong Kim
Initialize graphic and video input clocks in to safe frequency ranges. bug 966041 Change-Id: I48a035b42bad5a6d36f56e2b0610baf0703c3bcd Signed-off-by: Jong Kim <jongk@nvidia.com> (cherry picked from commit c33f503e768c44913af8d96898da43be05cdc01a) Reviewed-on: http://git-master/r/119792 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-08-02ARM: tegra: usb_phy: prevent illegal access to registersRakesh Bodla
Adding the conditions to prevent illegal register access. Bug 993380 Bug 1006579 Bug 1018601 Change-Id: Ifdeae6c8a16a87cf565ef7c954b363e9de885a20 Signed-off-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-on: http://git-master/r/113138 (cherry picked from commit a3c026a229bbce614d7f40319bada1d7bf42942d) Reviewed-on: http://git-master/r/117966 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Preetham Chandru <pchandru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Kiran Adduri <kadduri@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2012-07-25tegra: colibri_t20: decrease NAND clockMarcel Ziswiler
Looks like the older modules prior to V1.2 using Micron MT29F8G08ABCBB NAND flash parts have some timing issue. Decreasing the NAND flash controller clock from 144 back to 108 MHz seems to make it work again. Further investigation pending (e.g. explicitly setting timing mode 4).
2012-07-20tegra: colibri_t20: fbmem/nvmem handlingMarcel Ziswiler
Clean-up some obsolete init stuff while at it. Add note that V1.1c modules require proper BCT setting 666 rather than 721.5 MHz EMC clock in order for EMC scaling not to crash. Specify zero carveout argument to tegra_reserve() for special handling due to already reserved fbmem/nvmem. Requires our latest U-Boot 2011.06 from today which is compatible to both V1.x as well as V2.x images.
2012-07-20tegra: carveout and framebuffer memory sizingMarcel Ziswiler
Support fbmem in addition to tegra_fbmem kernel argument for backwards compatibility reason. Support nvmem kernel argument for carveout definition to be backward compatible. Add special handling in case of already reserved fbmem/nvmem.
2012-07-20tegra: colibri_t20: emc clean-upMarcel Ziswiler
Fix typo and get rid of obsolete 333 MHz SDRAM table entry.
2012-07-18tegra: fix usb_phy build breakage if gadget as moduleMarcel Ziswiler
Add missing symbol exports to address gcc 4.7.1 from oe-core throwing following errors if usb gadget stuff compiled as modules: ERROR: "tegra_usb_phy_memory_prefetch_on" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_memory_prefetch_off" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_charger_detect" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_power_off" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_close" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_power_on" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! ERROR: "tegra_usb_phy_open" [drivers/usb/gadget/fsl_usb2_udc.ko] undefined! While at it following build time warning addressed as well: arch/arm/mach-tegra/usb_phy.c: In function 'utmi_phy_postresume': arch/arm/mach-tegra/usb_phy.c:1678:16: warning: unused variable 'inst' [-Wunused-variable]
2012-07-18tegra: fix tegra_emc_to_cpu_ratio() if cpu runs > 1 GHzMarcel Ziswiler
Function erroneously checked the > 1 GHz case assuming cpu frequency being in Hz rather than kHz.
2012-07-16ARM: tegra: iovmm: Fix build error w/o CONFIG_IOVMMHiroshi DOYU
Update function prototype along with: commit 6cbf4c7465b7b70936cb422b509da0ad0829c306 ARM: tegra: iovmm: Allow alloc_client to take struct device Change-Id: I11d173429413ab268f6ab789d90f321e3d33de2c Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/115391 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-16ARM: tegra: iovmm: Make IOMMU/IOVMM selectable in KconfigHiroshi DOYU
This patch enables to replace iovmm*.ko family with tegra-{smmu,gart}.ko if needed in kernel config. To use IOMMU as backend engine, Enable TEGRA_IOMMU_{GART,SMMU} under IOMMU in config, and automatically disable IOVMM. IOVMM is equivalent to IOMMU_API. TEGRA_IOVMM_GART is equivalent to TEGRA_IOMMU_GART. TEGRA_IOVMM_SMMU is equivalent to TEGRA_IOMMU_SMMU. Change-Id: I73408e927eb3f21e1db4e73700aaf415f4949166 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/115011 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-16ARM: tegra: iovmm: Replace IOVMM backend with IOMMUHiroshi DOYU
Replace IOVMM backend functions with the standard IOMMU API ones. Instead of modifying the actual C-files in drivers, MACROs in iovmm.h does the all work. Change-Id: I27dc893555ca1495588852261e3ba1e3e5619764 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114460 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-13ARM: tegra: clock: Dynamically re-lock memory pllAlex Frid
So far Tegra3 EMC DFS allowed only scaling rates that can be divided down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM is always running at maximum SDRAM rate set at boot time, while PLLP rate 408MHz is fixed across all Tegra3 platforms. This commit implements dynamic re-locking of PLLM at run time. Now memory pll can lock either at boot rate or additional auxiliary rate that is selected as follows: auxiliary PLLM rate must be present in EMC DFS table, it must exactly match one of the rate steps for Tegra3 graphics bus with PLLC clock source (cbus), and must not be a proper factor of boot PLLM rate or PLLP fixed rate. When switching PLLM between boot and auxiliary rate, PLLC is used as backup memory pll, and during this time cbus is locked at auxiliary rate. In addition system bus is forced to temporarily use PLLP as a clock source (this is necessary as sbus main clock source is PLLM secondary divider PLLM_OUT1). Limitations: - only one auxiliary rate is supported, and it should be below PLLM boot rate, but above half of boot rate - dynamic re-lock is allowed only on LPDDR2 platforms - no clock other than EMC and system bus could use PLLM as a source; so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be selected, and VI clock (not covered by PLLM restricted configuration) must be moved to PLLP. Bug 1005576 Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/111438 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a) Reviewed-on: http://git-master/r/114760 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Increase boost_up_threshold for AVP clockVandana Salve
Increase the boost_up_threshold to 85 for ULP audio bug 1009849 Change-Id: I4b1b746f445f5c2804befa52ae95c69b6b467083 Signed-off-by: Vandana Salve <vsalve@nvidia.com> Reviewed-on: http://git-master/r/114620 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
2012-07-13ARM: tegra: cardhu: add mem 437MHz table for Samsung K4P8G304EBJihoon Bang
Bug 1005576 Signed-off-by: Peter Zu <pzu@nvidia.com> Reviewed-on: http://git-master/r/112036 (cherry picked from commit 1f1e6d22e771336fb9e0b91bbabf12fa89f0c57c) Change-Id: If65aba6aaa0a400c960a2d2b1315a07fa44dcefe Reviewed-on: http://git-master/r/115054 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2012-07-13ARM: tegra: change include to proper notationRhyland Klein
In this case we want to include a file in the same directory. We should be using "" with include instead of <>. This fixes a an issue using the chromeos toolchain (4.6.3+) where fuse.h is not found while compiling usb_phy.c. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Change-Id: I0c6bdf6768cd89740ed0444b2b46289057dfad6a Reviewed-on: http://git-master/r/114608 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-07-13ARM: tegra: clock: Allow Tegra3 PLLM rate changeAlex Frid
Allowed Tegra3 memory PLLM rate change, provided it is disabled. Since PLLM can deviate from boot configuration now, and on Tegra3 it is controlled by PMC override registers (not CAR module registers): - Re-factored PLLM initialization, resume, and set rate operations accordingly (enable and disable ops already used PMC override). - Made sure that boot configuration is restored on entry to LP0 to match memory timing saved in scratch registers. Bug 1005576 Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110937 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8) Reviewed-on: http://git-master/r/114759 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record EMC clock source rateAlex Frid
On Tegra3 added source rate to EMC clock source selection structure, and re-factored EMC DVFS initialization accordingly. Bug 1005576 Change-Id: I155e982bef2431a76cf5e5085070d4e654a7b49b Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110935 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bf52c26c532a9ebabc4fc8a1fb5fc9d88be85e66) Reviewed-on: http://git-master/r/114758 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Record shared bus backup rateAlex Frid
Added shared bus backup rate entry to clock descriptor; initialized it for cbus (currently the only shared bus with backup source). Bug 1005576 Change-Id: I8124aa87f1dc307e42417da8f78797cfaf71e5dc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/110934 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> (cherry picked from commit bc5ed688929c3c0ca920b5e9663cf9c6fb85c00f) Reviewed-on: http://git-master/r/114757 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-13ARM: tegra: clock: Adjust Tegra3 cpu to emc ratioAlex Frid
On Tegra3 changed cpu rate threshold for maximum emc rate request from 750MHz to 925MHz. Adjusted cpu frequency table to provide entries close to the new threshold for all Tegra3 skus. Bug 998044 Bug 1003521 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I6e6df1958db9d55ad64cf35a5e9fe6ec74b8d4ea Reviewed-on: http://git-master/r/106946 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2012-07-12arm: tegra: kai: fix time does not increase in lp0Chandler Zhang
time does not increase in LP0 because GPIO4 is configured as POR. Change to active_low and pull push to fix the issue. Bug 1014548 Change-Id: I13c65ac6a4f3ae9158c58922e1ad6982f24bb103 Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/114866 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Jinyoung Park <jinyoungp@nvidia.com> Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
2012-07-12ARM: Tegra: cardhu: No longer invert backlight on PM313Graziano Misuraca
Backlight value was inverted for panels with PM313. This assumed the panel was the 15", but because the 10.1" (AUO) is more prevalent and doesn't have the inverted backlight signal we no longer need to invert it. Note this will fix the backlight issue for AUO E1198 boards but break it for 15". Bug 962636 Reviewed-on: http://git-master/r/#change,93965 Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com> Change-Id: Icb65592eb2df21e349e5a759a780e4438a0f5b26 Reviewed-on: http://git-master/r/95728 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11arm: tegra: pm269: 12.75mhz emc rateWen Yi
Add 12.75mhz emc frequency for Samsung K4P8G304EB-FGC2 LPDDR2 1GB memory chip. Bug 1011100 Change-Id: Ibbbb3f002c36c31cd2806051803ddd3ba9daa63b Signed-off-by: Wen Yi <wyi@nvidia.com> (cherry picked from commit a37cb14dc441005ddd977b6a83f41df817179d79) Reviewed-on: http://git-master/r/113383 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11arm: tegra: cardhu: move VI to PLL_PJihoon Bang
As a part of effort to bring in 437MHz clock frequency in EMC, We need to move VI from PLL_M to PLL_P. Bug 1005576 Signed-off-by: Jihoon Bang <jbang@nvidia.com> Reviewed-on: http://git-master/r/112704 (cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835) Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e Reviewed-on: http://git-master/r/114241 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11ARM: tegra: iovmm: Allow alloc_client to take struct deviceHiroshi DOYU
Allow tegra_iovmm_alloc_client() to take struct device * instead of const char *name w/ __tegra_iovmm_alloc_client(). This is necessary to support IOVMM and IOMMU simultaneously. Change-Id: I18df5001bfe0ece8f9f15b636eb11def9f228dfb Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114215 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: iomap: Introduce TEGRA_IOMMU_{BASE,SIZE} for SMMU/GARTVandana Salve
Replace TEGRA_{SMMU,GART}_{BASE,SIZE} with TEGRA_IOMMU_{BASE,SIZE} to deal with SMMU/GART in unified manner. This is necessary for DMA mapping API to pass the appropriate IOMMU address for SMMU and GART in the same code in nvmap. [Hiroshi Doyu: Squash nvmap parts into "nvmap: API conversion" patch.] Change-Id: I75429dd56554f880f144c375d2c20e8e8948ceee Signed-off-by: Vandana Salve <vsalve@nvidia.com> Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11arm: tegra: p1852: Add IOMMU_SMMU supportHiroshi DOYU
Migrating from IOVMM_SMMU to IOMMU_SMMU. Change-Id: If5bca4a3bce15d59641f11dfea3ad6da2a8efbf5 Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/114211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-07-11ARM: tegra: Remove duplicate clock initsSai Charan Gurrappadi
Change-Id: I80c384d1aa4b1e45a4542acbde6b904f4a014aff Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com> Reviewed-on: http://git-master/r/113679 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> GVS: Gerrit_Virtual_Submit
2012-07-11ARM: tegra: thermal: fixed some skin thermal bugsJoshua Primero
Fixed bug where skin cooling device is being bound to nct device instead of skin thermal device. bug 1007726 Change-Id: Ia6316735da8895fd4f4c20c0a76cd6796dafdf9b Signed-off-by: Joshua Primero <jprimero@nvidia.com> Reviewed-on: http://git-master/r/113563 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11ARM: tegra: cardhu: disable VBUS wakeBitan Biswas
Disabled USB1 VBUS wake up on board revisions prior to E1291-A03 and E1198-A02. We see repeated LP0 wakeups if the wake source is enabled. bug 980993 Change-Id: I080696924aaea06f973392fe7682fecc7574bf02 Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103627 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-07-11ARM: tegra: support multiple wake sources with same irqBitan Biswas
Earlier implementation only allowed single wake source for a particular irq in wake table. Changed implementation to support multiple wake sources ==> single irq mapping. bug 980993 Change-Id: Iacb00487531129ef19c53128824aba802e80350e Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/103140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-07-09arm: tegra: kai: use regulator to control vbusChandler Zhang
Use regulator instead of USB OTG callback to control USB VBUS. Bug 997805 Change-Id: Icd2869f51e312c52b272a6e32fa8c7ab8763a5ac Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/112900 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: tegra: fiq_dbg: Enable FIQ serial debugKamal Kannan Balagopalan
Add platform callback to initialize and enable FIQ serial debugger Bug 970018 Change-Id: Icdf571f7698e10de661a0ce94694de9fb9c70271 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/110955 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09arm: tegra3: usb_phy: Fix warning message for lp1 resumePreetham Chandru
When the system resumes from lp1 for usb wake event we are seeing the below warning message: usb_phy_bringup_host_controller: timeout waiting for PORT_SUSPEND The above warning message are seen only for lp1 resume and not for lp0 resume. This is happening only for lp1 resume because in usb_phy_bringup_host_controller(), the port is suspended only if we are not resuming from remote wakeup, in case of lp0 remote_wake flag is set to true but not in case of lp1. This is because in lp1, pmc is not responsible for waking the system but it's the flow controller and hence UTMIP_WALK_PTR_VAL(inst) will return 0 due to this remote wakeup flag was getting reset to false. Bug 985396 Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Change-Id: I67fcf21d77cbc627315164b6e1c4f27b0b9ae2c3 Reviewed-on: http://git-master/r/110064 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: tegra: wdt: Remove legacy WDT device supportKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Remove the obsolete legacy WDT support for Tegra3 Bug 857748 Change-Id: I82478e1b43f22f39c1b8e6e66ae5299ffd079d1b Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/109908 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09ARM: tegra: wdt: Replace legacy WDT with CPU WDTsKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Replace legacy WDT with CPU WDTs in all Tegra3 platforms. Bug 857748 Change-Id: I5bd30687003e6b2ebf09916fbd626d82f0bc0b76 Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/109907 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-07-09arm: tegra: fix power down sequence fps/ameChandler Zhang
Fix power down sequence to align with POR. FPS, GPIO and AME part. LDO4 tracking is not disabled. Affcted regs: FPS_SD3 FPS_SD2 FPS_SD1 FPS_L4 FPS_L3 AME_GPIO GPIO3 GPIO4 CNFG1_L4 CNFG1SD0 CNFG1SD1 Bug 1001267 Change-Id: I8db160bf00cbe8f215c6e1b762d994d26d82809f Signed-off-by: Chandler Zhang <chazhang@nvidia.com> Reviewed-on: http://git-master/r/109134 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2012-07-09ARM: tegra: wdt: Add support for Tegra3 CPU WDTsKamal Kannan Balagopalan
Tegra3 adds new CPU watchdog timers. Add device support for the CPU WDTs. Bug 857748 Change-Id: I0f99c37fed89879d39667b734654c659fe631aaf Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com> Reviewed-on: http://git-master/r/108379 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-19 08:40:10 +0000