Age | Commit message (Collapse) | Author |
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Tegra20 and Tegra30 do not support gen2 PCIe, so correct the
register setting to disable it.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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Conflicts:
drivers/media/video/tegra_v4l2_camera.c
reverted to current driver supporting ACM rather than CSI2
drivers/media/video/videobuf2-dma-nvmap.c
drivers/video/tegra/host/Makefile
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Activate Fusion touchscreen driver. Use GPIO 5/6 as pen down/reset
GPIO and provide a helper function to free the GPIO before the
driver requests them.
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Fusion touchscreen driver now uses platform data to do GPIO
initialization by itself. Make use of this by providing GPIO numbers
instead of doing initialization in the board initialization.
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Allow to change clock polarity for RGB display output using the
keywords outputen/pixclockpol/vsync and hsync. Add them right
after the driver specification, use 0/1 to specifiy high/low
polarity, e.g. video=tegrafb0:pixclockpol:1,800x480
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Remove special clocks for Tegra 2, but use backup clock source
instead. This allows to run all common used resolution within
the drivers -1/+9% allowed band for pixelclock exactness.
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Remove TEGRA_FB_VGA defines and use VGA as default. Since initial
mode is now configureable through kernel cmd line parameter, we
don't need those compile time helpers.
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Use modedb to set mode on framebuffer/display controller for
Tegra 20 based module Colibri T20 too.
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In order to find a viable resolution we not only parse VESA mode,
we also parse CEA (multimedia) modes and our own small modedb (for
specific touch screens).
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Use new modedb based framebuffer settings by defining default_mode
in the display controllers platform data. Also impelmented the
fallback logic to this default_mode in case no kernel cmd line
parameter was set.
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Allow to specify framebufffer videomode using kernel command line
parameters. NVIDIAs binary X driver later on picks up those settings
and start X with current mode settings, if no EDID data are available.
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Make use of the new STMPE ADC driver to expose the four free ADC
channels on the STMPE811 to userspace.
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The drivers internal root_bus_nr used to be u8 which lead to a wrong
error detection in bus_to_port. Bus number can be -1 in case bus is
not scanned yet. Thanks to James pointing that out.
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The port used for KEY_BACK does not support wakeup (no wake PIN). Remove
the wake flag, this prevents unbalanced irq warning messages.
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Add GPIO keyboard platform device configuration. Currently only the power key
is defined which is registred as wake key as well in order to wake the SoC when
in sleep mode (MXM3 37/WAKE1_MICO).
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SKU 0x81 is identical to 0xB1 so same can be used
for sku to speedo ID conversion.
Bug 1313434
Change-Id: I63f08522878524a05c2a6fb0a82fee90a59a99bd
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/334396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Remove vdd_hdmi_con regulator from dc1 since we don't have a dedicated
regulator for this connector on our baseboards.
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Use TPS6591X IRQ base define to calculate correct IRQ number.
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Use TPS6591X base defines to make sure the chip gets its own irq range rather
than interfer with the STMPE chip.
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Clean-up GPIO definitions and names (e.g. use LVDS_ defines, BKL1_ON
rather than BL_ON and HDMI1_HPD rather than hdmi_hpd).
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This gives the DDR3L memory settings for 400MHz/800MHz.
The boot memory speed must be 400MHz for this to work, i.e.
the 400MHz BCT must be used.
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Enable OV5650 and OV5640 sensor in Cardhu board file with the help of
Tegra V4L2 SoC camera interface.
To use V4L2 driver, we need to disable old camera HAL driver.
Bug 1240806
Bug 1369083
Change-Id: I0dc529d44fba4d80b45690e384e8bf81b29f69e5
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246266
(cherry picked from commit 6b2f7cc4117208dc992478f27d5873ea38071fdc)
Reviewed-on: http://git-master/r/279988
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Configure pll_a during boot so that
locking to pll_a does not fail
Bug 1330751
Change-Id: I188f0be211379f43770b24c5b382dec2788aefda
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/269469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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DVFS entry is fixed for Hynix_2GB_H5TC4G83MFR-PBA
to support all emc frequencies.
Bug 1218885
Change-Id: Id9d578499e495f43db1a072cbcee25a353fa78f5
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/210653
(cherry picked from commit 688bf04ff67e2c1ff22762f4f578b925ff3b9f3c)
Reviewed-on: http://git-master/r/273530
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Up to now only the LVDS transceiver controlling GPIOs were exported.
This patch adds the generic Apalis GPIOs to the list of via sysfs to
userspace exported ones as well.
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Initialisation of the framebuffer console on DVI-D aka HDMI sometimes
failed. This was particularly bad on Apalis T30 where this is activated
by default. On Colibri T30 this was observed when enabling it using the
fbcon=map:1 boot argument.
This fix curtsey of Bibek Basu from NVIDIA explicitly enables PLLA
during early clock initialisation which avoids a later race with the
display driver on DC1.
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In preparation for the new Apalis resp. Colibri T30 production lots
with either T30IQS-P-A3 or T30MQS-P-A3 chips that due to some bug were
locked at 312 MHz force a speedo ID of 2 for now which allows regular
operation of up to 1.4 GHz (single core only).
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Allow for jumper-less ACM operation by defaulting to 0x20 I2C address.
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This patch fixes building without CONFIG_SATA_AHCI_TEGRA aka SATA
support which previously failed as follows:
...
CC arch/arm/mach-tegra/board-apalis_t30.o
~/linux-toradex/arch/arm/mach-tegra/board-apalis_t30.c:571:31: error:
'apalis_led_gpio_device' defined but not used [-Werror=unused-variable]
cc1: all warnings being treated as errors
make[2]: *** [arch/arm/mach-tegra/board-apalis_t30.o] Error 1
make[1]: *** [arch/arm/mach-tegra] Error 2
make[1]: *** Waiting for unfinished jobs....
make: *** [sub-make] Error 2
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If the local critical temperature is reached the power is
unconditionally switched off. At 70°C ambient the default of 85°C
can be reached. So increase the limit in the hwmon chip to 95°C.
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If the local critical temperature is reached the power is
unconditionally switched off. At 70°C ambient the default of 85°C
can be reached. So increase the limit in the hwmon chip to 95°C.
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Enable PCI quirk support resp. don't explicitly disable it in order for
the following fix to take effect.
The Apalis evaluation board needs to set the link speed to 2.5 GT/s
(GEN1). The default link speed setting is 5 GT/s (GEN2). 0x98 is the
Link Control 2 PCIe Capability Register of the PEX8605 PCIe switch. The
switch supports link speed auto negotiation, but falsely sets the link
speed to 5 GT/s.
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Integrate ADV7180 and MAX9526 video decoder support and prepare for
drivers as modules.
The following gstreamer pipeline shows a preview window:
gst-launch v4l2src ! deinterlace tff=1 method=4 ! nv_omx_videomixer !
nv_gl_eglimagesink
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Integrate ADV7180 and MAX9526 video decoder support and prepare for
drivers as modules.
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Remove tegra_aes_device from the platform device list as it was listed
twice.
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Integrate ADV7180 video decoder support.
While at it prepare for ADV7180 as well as MAX9526 drivers as module.
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Avoid AXI response decoding errors of the following form by properly
setting the root bus number:
[ 3.377991] PCIE: AXI response decoding error, signature: ff01003d
[ 3.384174] PCIE: AXI response decoding error, signature: ff01003c
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Implement workaround for PLX PEX 8605 errata 5 (PEX_REFCLK_OUTpx/nx
Clock Outputs is not Guaranteed Until 900 us After PEX_PERST#
De-assertion) by releasing RESET_MOCI_N 1 ms after releasing
PEX_PERST_N.
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Add a comment about conflicting use of SODIMM pin 150 as GPIO K0 resp.
GMI_ADV_N used for multiplexed address/data bus courtesy of Stéphane
Gonnella from Multitel ASBL.
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Revert the following commit:
4bb48c289cdfddf02673b5b3dd1a735dfd5d972e
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Added skeleton code to define userspace accessable gpio.
Export gpios which are unlikely to be used for other functions.
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This change is intended to add a few modifications to
cardhu board file (which is also used for beaver)
to get rid of NACK errors occuring due to the absence
of certain hardware components on beaver
Bug 1217572
Change-Id: I1df7b7f777014610e4d64695d89324808ea4f266
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/215983
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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Enable the back key as a wake-up source as well.
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Use 32 rather than 16 bits per pixel as otherwise it looks so ugly.
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Due to 720p not working well with most regular analogue screens and as
customers rather might want to evaluate using our 7 inch EDT
ET070080DH6 panel revert to 800x480 if not default VGA TFTLCD
resolution is chosen.
This reverts commit 0fc41ea361c79175f2076a349a0ba0dcc7e71131.
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