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2012-06-13Avoid aliasing mappings in DMA coherent allocatorManoj Chourasia
Avoid multiple mappings with DMA coherent/writecombine allocator by pre- allocating the mappings, and removing that memory from the system memory mapping. (See previous discussions on linux-arm-kernel as to why this is bad.) NB1: By default, we preallocate 2MB for DMA coherent, and 2MB for write combine memory, rather than 1MB for each in case 1MB is not sufficient for existing platform usage. Platforms have the option of shrinking this down to 1MB DMA / 1MB WC (or even 2MB DMA / 0MB WC) if they so wish. The DMA memory must be a multiple of 1MB, the write combine memory must also be a multiple of 1MB, and the two together must be a multiple of 2MB. NB2: On ARMv6/7 where we use 'normal uncacheable' memory for both DMA and WC, the two pools are combined into one, as was the case with the previous implementation. The down side to this change is that the memory is permanently set aside for DMA purposes, but I believe that to be unavoidable if we are to avoid the possibility of the cache getting in the way on VIPT CPUs. This removes the last known offender (at this time) from the kernel. Given that DMA memory is fully coherent by this patch, cache invalidation/clean is not required and so, we skip cache related activities for the memory managed by the DMA layer. The bus address -> virtual address conversion normally used in the calling path and the fact that we remove kernel static mapping corresponding to the DMA buffers leads to exceptions otherwise. bug 876019 bug 965047 bug 987589 Change-Id: I72beb386605aafe1a301494a95a67d094ea6b2e4 Signed-off-by: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com> Reviewed-on: http://git-master/r/106212 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2012-06-07mm: Ensure pte and pmd stores ordering.Krishna Reddy
Bug 974153 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Change-Id: I294a93eca0b395c8c2639a7d6a2d29c54447ae37 Reviewed-on: http://git-master/r/105215 Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Vinod Rex <vrex@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-05-04ARM: errata: 716044: an uncacheable load multiple can cause a deadlock.Krishna Reddy
Under some rare circumstances, an uncacheable load multiple instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause a processor deadlock. Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/95914 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2012-04-24ARM: mm: cache-l2x0: use L2X0_CACHE_ID_PART_MASK to get cache-idVarun Wadekar
l2x0_unlock does not use L2X0_CACHE_ID_PART_MASK to get the actual cache-id, thus always iterating over only one I and one D lockdown register. Change-Id: If473bd32991a6a97f9da6b8712f297a8bd00d32e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/96954 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2012-04-19Revert "ARM: pm: preallocate a page table for suspend/resume"Sang-Hun Lee
This reverts commit 55f0f45a45263ba26bd473f50f867d29dd836e46. Bug 967887 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Change-Id: I036e0bd4e391a17dec8fa0fe86da7eb6b98d503a Reviewed-on: http://git-master/r/96795 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: pm: only use preallocated page table during resume"Sang-Hun Lee
This reverts commit 46d9f14943770c24603ef7cdfd8eb2dbcd3c1248. Bug 967887 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Change-Id: Iee732d8137043240902201d7783d2c3fede98fbe Reviewed-on: http://git-master/r/96794 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-19Revert "ARM: pm: no need to save/restore context ID register"Sang-Hun Lee
This reverts commit 16e0bb8c46656b1d902d422e0065c746af161a1c. Bug 967887 Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Change-Id: Ifa115c4030c48cbd0b629cf02899ca8c6f25d314 Reviewed-on: http://git-master/r/96792 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-04-05ARM: pm: no need to save/restore context ID registerRussell King
There is no need to save and restore the context ID register on ARMv6 and ARMv7 with a temporary page table as we write the context ID register when we switch back to the real page tables for the thread. Moreover, the temporary page tables do not contain any non-global mappings, so the context ID value should not be used. To be safe, initialize the register to a reserved context ID value. Change-Id: I7de05e736dde5bc1b8ab682a8660eaaba52104cf Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/85727 Reviewed-by: Automatic_Commit_Validation_User
2012-04-05ARM: pm: only use preallocated page table during resumeVarun Wadekar
Only use the preallocated page table during the resume, not while suspending. This avoids the overhead of having to switch unnecessarily to the resume page table in the suspend path. Change-Id: Ib71c9b60b0ec39749aadc6f592549d213e6a852e Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/85725 Reviewed-by: Automatic_Commit_Validation_User
2012-04-05ARM: pm: preallocate a page table for suspend/resumeRussell King
Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Change-Id: I625d3622359e961e4f358171e9a82b51bcecf9c2 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/85671 Reviewed-by: Automatic_Commit_Validation_User
2012-03-12ARM: mm: Use CONFIG_CPAKrishna Reddy
Use CONFIG_CPA flag to allow disabling CPA code. Change-Id: Ic6a4993dbabbef8d9847295f698887d73d81269a Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/88464 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2012-03-09cache-v7: Fix typoDan Willemsen
Change 6dfe0d880a was backported from upstream, but differed from the upstream patch with a typo - CONFIG_PREEMP vs CONFIG_PREEMPT Change-Id: Ib8dea88cfc4d85bc6a3873acd4152bc628c03bb0 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-on: http://git-master/r/85059 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
2012-03-08ARM: mm: Add config flag for CPA.Krishna Reddy
Change-Id: Ibaa40012b3954abb440882517de51ab37269942f Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/88183 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
2012-03-07ARM: mm: Implement complete debug arch v7 save/restoreScott Williams
Implement the complete debug arch v7 save/restore sequence as required by the ARM Architectural Reference Manual. Change-Id: Ia346a87b16e759ae5dbbbd02e77eda1e6d6deb82 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/87865 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
2012-03-02arm: cache: fix v7 boot with lockdep enabledPrashant Gaikwad
Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Change-Id: I1110a7e07fa3f96022b2e198488fa698c91e2642 Reviewed-by: Nicolas Pitre <(address hidden)> Acked-by: Stephen Boyd <(address hidden)> Cc: Catalin Marinas <(address hidden)> Cc: stable@vger.kernel.org Signed-off-by: Rabin Vincent <(address hidden)> Reviewed-on: http://git-master/r/86779 Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
2012-03-01ARM: mm: Make CPU debug context save/restore optionalScott Williams
Change-Id: I5a5a26c6fc0a169a004307e07de1223c107e4df7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/86158 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Gerrit_Virtual_Submit
2012-02-15cache-v7: Disable preemption when reading CCSIDRStephen Boyd
armv7's flush_cache_all() flushes caches via set/way. To determine the cache attributes (line size, number of sets, etc.) the assembly first writes the CSSELR register to select a cache level and then reads the CCSIDR register. The CSSELR register is banked per-cpu and is used to determine which cache level CCSIDR reads. If the task is migrated between when the CSSELR is written and the CCSIDR is read the CCSIDR value may be for an unexpected cache level (for example L1 instead of L2) and incorrect cache flushing could occur. Disable interrupts across the write and read so that the correct cache attributes are read and used for the cache flushing routine. We disable interrupts instead of disabling preemption because the critical section is only 3 instructions and we want to call v7_dcache_flush_all from __v7_setup which doesn't have a full kernel stack with a struct thread_info. This fixes a problem we see in scm_call() when flush_cache_all() is called from preemptible context and sometimes the L2 cache is not properly flushed out. Signed-off-by: Stephen Boyd <(address hidden)> Acked-by: Catalin Marinas <(address hidden)> Reviewed-by: Nicolas Pitre <(address hidden)> Cc: stable@vger.kernel.org Change-Id: I34a54ac396929d9e4f9abb43fbeaeb71d5514b63 Reviewed-on: http://git-master/r/83094 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
2012-02-09ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guardsWill Deacon
commit 612539e81f655f6ac73c7af1da8701c1ee618aee upstream. On v7, we use the same cache maintenance instructions for data lines as for unified lines. This was not the case for v6, where HARVARD_CACHE was defined to indicate the L1 cache topology. This patch removes the erroneous compile-time check for HARVARD_CACHE in proc-v7.S, ensuring that we perform I-side invalidation at boot. Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Catalin Marinas <Catalin.Marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I9a44ed525f4f702f9fac2965828608d9f1865633 Reviewed-on: http://git-master/r/79664 Reviewed-by: Automatic_Commit_Validation_User
2012-01-19arm: mm: Optimze cache flush in CPA.Krishna Reddy
Optimze cache flush time and enable cache flush for high mem pages in CPA. Bug 865816 Change-Id: I15736010bd26c18ea0d3350c15769675f07ac055 Reviewed-on: http://git-master/r/71725 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/75880 Reviewed-by: Automatic_Commit_Validation_User
2011-12-23arm: mm: Fix CPA page count stats issue.Krishna Reddy
Bug 865816 Change-Id: Iebdfdbd650cb82f25487ebee1c2b3839ed1fcf94 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/71729 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2011-12-15arm: mm: convert cpa_lock to mutex.Krishna Reddy
convert cpa lock to mutex from spin lock. This is needed as page allocs, which can sleep, are happening inside the spinlock. Bug 913652 Change-Id: I8a31e31c2ca8f7631ec626a82a74509494f47219 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/69517 Reviewed-by: Automatic_Commit_Validation_User
2011-12-08arm: tegra: add Trusted Foundations hooks and driverChris Johnson
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
2011-11-30fixup l2x0 variable nameDan Willemsen
Rebase-Id: R6f9abcf82f732ac856451f20e29bf173908a28c7
2011-11-30Merge branch 'korg-android-tegra-3.1' into after-upstream-androidDan Willemsen
Conflicts: arch/arm/mach-tegra/Kconfig arch/arm/mach-tegra/board-ventana.c drivers/misc/Kconfig drivers/video/tegra/dc/hdmi.c Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-30arm: dma: Drop GFP_COMP for DMA memory allocationsSumit Bhattacharya
dma_alloc_coherent wants to split pages after allocation in order to reduce the memory footprint. This does not work well with GFP_COMP pages, so drop this flag before allocation. This patch is ported from arch/avr32 (commit 3611553ef985ef7c5863c8a94641738addd04cff). Change-Id: I455cfdc7a2180b8d9d193da5fc8aaf70f8b94ee2 Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-on: http://git-master/r/57854 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: Rff955dbdf67e8222f9640910124c5ed2eb600f5a
2011-11-30arm: mm: change_page_attr supportVinod Rex
bug 865816 Adapted from x86 change_page_attr() implementation Change-Id: I398c9d460b841484de4fcfcac10ffffdf49a4a5a Reviewed-on: http://git-master/r/56769 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: Rddeccf358c948ba84af52316f084814ae53dca5e
2011-11-30ARM: mm: Enable Arm errata 743622 for Cortex-A9 versions r2p7 and r2p9.vdumpa
(cherry picked from commit 995e965d413847e0b76560e7cf8a4741b13ec4a8) Change-Id: Ie44536006407bce50d0c25c955fd37c5782548fe Reviewed-on: http://git-master/r/54096 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R7ef13a653c90d255f5c62df9456b69df187457d6
2011-11-30ARM: errata: 752520: Faulty arbitration between PLD and Cacheable TLB ↵vdumpa
requests may create a system deadlock. Under rare circumstances, PLDs may interfere with a Cacheable page table walk, creating a processor deadlock. The erratum can only happen when the Data Cache and MMU are enabled, with the TLB descriptors marked as L1 cacheable, so that Page Table Walks are performed as cache linefills. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing PLD operations treated as NOP. (cherry-picked from b501cafea7328bc578f67e3e846ab9d25b7ec1b0) Change-Id: Ic4039b83de43530bae7ce705162441bea74e1e98 Reviewed-on: http://git-master/r/54095 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: Ra35e48e21c1d62b6480a9d67d1413dd5d0df3f53
2011-11-30ARM: remove unnecessary dcache_clean_areaHeechul Yun
Cortex-A9 has PIPT D-cache which do not require clean the cache on creating page table. Original-Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980 Reviewed-on: http://git-master/r/40505 Reviewed-by: Heechul Yun <hyun@nvidia.com> Tested-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R214ce4b138abb18e1cfe79465087c39ead248d72
2011-11-30arm: mm: Remove unnecessary cache flush on page table modificationHeechul Yun
Since MMU of Cortex-A9 read from L1-D not from memory, there's no need to flush the cache line of the modified page table entry. Original-Change-Id: Ie5e6a027f633ed6060b8d2a9fdcd6a5399736d55 Reviewed-on: http://git-master/r/39697 Reviewed-by: Heechul Yun <hyun@nvidia.com> Tested-by: Heechul Yun <hyun@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: Rb8fd18147f8eb30b7969a6eac490efe03b646f16
2011-11-30ARM: v7: Save CP14 registers across suspendScott Williams
Change-Id: I48bd9ddf9f0a65b1754560bae261d0b3faa69e06 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: Rbbd2387b98c81919b3a8bf9782828c8b4ef33f45
2011-11-30ARM: v7: Save CP15 diagnostic register across suspendScott Williams
Change-Id: I7d0efeb53e41722f92f9373785045ccc61e56adf Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R6ab8cf0cfe2930330b49d3fccee65d8366ef909d
2011-11-30Merge branch 'buckets/video' into after-bucketsDan Willemsen
2011-11-30tegra:video:nvmap: optimize cache_maint operation.vdumpa
video:tegra:nvmap: Clean whole L1 instead of cleaning by MVA For large allocations, cleaning each page of the allocation can take a significant amount of time. If an allocation that nvmap needs to clean or invalidate out of the cache is significantly larger than the cache, just flush the entire cache by set/ways. bug 788967 Reviewed-on: http://git-master/r/19354 (cherry picked from commit c01c12e63b1476501204152356867aeb5091fb80) tegra:video:nvmap: optimize cache_maint operation. optimize cache_maint operation for carveout and heap memories. flush carveout memory allocations on memory free. Bug 761637 Reviewed-on: http://git-master/r/21205 Conflicts: drivers/video/tegra/nvmap/nvmap_dev.c drivers/video/tegra/nvmap/nvmap_heap.c drivers/video/tegra/nvmap/nvmap_ioctl.c (cherry picked from commit 731df4df5e895e1d4999359d6d5939fc2095f883) tegra:video:nvmap: optimize cache flush for system heap pages. optimize cache flush for pages allocated from system heap. Bug 788187 Reviewed-on: http://git-master/r/21687 (cherry picked from commit 3f318911ad91410aed53c90494210e2b8f74308b) Original-Change-Id: Ia7b90ba0b50acfef1b88dd8095219c51733e027f Reviewed-on: http://git-master/r/23465 Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com> Tested-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R04f618f88ed1d2c7a680d51a8c5113f42de3f667
2011-11-30tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributesvdumpa
Change the cacheability attributes in the normal memory remap register (NMRR) to inner write-back write-allocate/outer write-back no-write-allocate to improve L2 cache performance. Bug 728231 Bug 751146 Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d Reviewed-on: http://git-master/r/11077 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-on: http://git-master/r/17475 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7 Rebase-Id: R430708cbf798ff30f5a5394a5235942e95bda2d4
2011-11-30ARM: Cortex-A9: Enable dynamic clock gatingTodd Poynor
Enable dynamic high level clock gating for Cortex-A9 CPUs, as described in 2.3.3 "Dynamic high level clock gating" of the Cortex-A9 TRM. This may cut the clock of the integer core, system control block, and Data Engine in certain conditions. Add ARM errata 720791 to avoid corrupting the Jazelle instruction stream on earlier Cortex-A9 revisions. Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86 Signed-off-by: Todd Poynor <toddpoynor@google.com> Rebase-Id: R7ae4d4825e9171bca2471fe776ecf363e75b9ca6
2011-11-30Merge branch 'korg-android-3.1' into korg-android+linux-tegra-3.1Dan Willemsen
Conflicts: arch/arm/mm/cache-l2x0.c drivers/misc/Kconfig drivers/misc/Makefile Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2011-11-30ARM: cache-l2x0: update workaround for PL310 errata 727915Colin Cross
ARM errata 727915 for PL310 has been updated to include a new workaround required for PL310 r2p0 for l2x0_flush_all, which also affects l2x0_clean_all in my testing. For r2p0, clean or flush each set/way individually. For r3p0 or greater, use the debug register for cleaning and flushing. Requires exporting the cache_id, sets and ways detected in the init function for later use. Change-Id: I215055cbe5dc7e4e8184fb2befc4aff672ef0a12 Signed-off-by: Colin Cross <ccross@android.com>
2011-11-30[ARM] Optionally flush entire dcache from v6_dma_flush_rangeArve Hjønnevåg
If CACHE_FLUSH_RANGE_LIMIT is defined, then the entire dcache will be flushed if the requested range is larger than this limit. Change-Id: I29277d645a9d6716b1952cf3b870c78496261dd0 Signed-off-by: Arve Hjønnevåg <arve@android.com>
2011-11-30[ARM] mm: add memory type for inner-writebackColin Cross
For streaming-style operations (e.g., software rendering of graphics surfaces shared with non-coherent DMA devices), the cost of performing L2 cache maintenance can exceed the benefit of having the larger cache (this is particularly true for OUTER_CACHE configurations like the ARM PL2x0). This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1) in the tex remapping tables as an inner-writeback-write-allocate, outer non-cacheable memory type, so that this mapping will be available to clients which will benefit from the reduced L2 maintenance. Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com> Conflicts: arch/arm/include/asm/pgtable.h arch/arm/mm/proc-v7.S
2011-11-30Revert "[ARM] mm: add page allocator for modifying cache attributes"Gary King
This reverts commit 54d414570432ce07fa1a14b657f53bed752e3d7e. Change-Id: I8e5cf6ef3555129da9741ef52a1e6a3a772ad588 Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30[ARM] attrib_alloc: fix outer cache flush end addressGary King
when allocating uncached pages, the outer cache should be flushed; the end address should be specified in bytes, not in pages. Change-Id: I3fe036f4f7e10e009f96567e3afeeef6ea603240 Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30[ARM] mm: add page allocator for modifying cache attributesGary King
ARM CPUs with speculative prefetching have undefined behaviors when the same physical page is mapped to two different virtual addresses with conflicting cache attributes. since many recent systems include IOMMU functionality (i.e., remapping of discontiguous physical pages into a virtually-contiguous address range for I/O devices), it is desirable to support allocating any available OS memory for use by the I/O devices. however, since many systems do not support cache coherency between the CPU and DMA devices, these devices are left with using DMA-coherent allocations from the OS (which severely limits the benefit of an IOMMU) or performing cache maintenance (which can be a severe performance loss, particularly on systems with outer caches, compared to using DMA-coherent memory). this change adds an API for allocating pages from the OS with specific cache maintenance properties and ensures that the kernel's mapping of the page reflects the desired cache attributes, in line with the ARMv7 architectural requirements Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0 Signed-off-by: Gary King <gking@nvidia.com>
2011-11-30ARM: mm: cache-l2x0: Add support for re-enabling l2x0Colin Cross
Remove __init annotation from l2x0_init so it can be used to reinitialize the l2x0 after it has been reset during suspend. Only print the init messages the first time l2x0_init is called. Add l2x0_enable to re-enable the l2x0 after l2x0_disable if the l2x0 was not reset. l2x0_disable cannot use writel, as writel calls wmb(), and wmb() may call outer_cache_sync, which takes the same spinlock as l2x0_disable. Change-Id: Iaddedb4f582c7eeaef3cbe2a1e463787f0f809a4 Signed-off-by: Colin Cross <ccross@android.com>
2011-10-01ARM: 7113/1: mm: Align bank start to MAX_ORDER_NR_PAGESLinus Walleij
The VM subsystem assumes that there are valid memmap entries from the bank start aligned to MAX_ORDER_NR_PAGES. On the Ux500 we have a lot of mem=N arguments on the commandline triggering this bug several times over and causing kernel oops messages. Cc: stable@kernel.org Cc: Michael Bohan <mbohan@codeaurora.org> Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Johan Palsson <johan.palsson@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26ARM: dma-mapping: free allocated page if unable to mapRussell King
If the attempt to map a page for DMA fails (eg, because we're out of mapping space) then we must not hold on to the page we allocated for DMA - doing so will result in a memory leak. Cc: <stable@kernel.org> Reported-by: Bryan Phillippe <bp@darkforest.org> Tested-by: Bryan Phillippe <bp@darkforest.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-17ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeedWill Deacon
This patch implements a workaround for erratum 764369 affecting Cortex-A9 MPCore with two or more processors (all current revisions). Under certain timing circumstances, a data cache line maintenance operation by MVA targeting an Inner Shareable memory region may fail to proceed up to either the Point of Coherency or to the Point of Unification of the system. This workaround adds a DSB instruction before the relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. Cc: <stable@kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-10ARM: 7088/1: entry: fix wrong parameter name used in do_thumb_abortJanusz Krzysztofik
Commit be020f8618ca, "ARM: entry: abort-macro: specify registers to be used for macros", while replacing register numbers with macro parameter names, mismatched the name used for r1. For me, this resulted in user space built for EABI with -march=armv4t -mtune=arm920t -mthumb-interwork -mthumb broken on my OMAP1510 based Amstrad Delta (old ABI and no thumb still worked for me though). Fix this by using correct parameter name fsr instead of mismatched psr, used by callers for another purpose. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-07ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij
Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-04ARM: 7067/1: mm: keep significant bits in pfn_validMark Rutland
When ARCH_HAS_HOLES_MEMORYMODEL is selected, pfn_valid calls memblock_is_memory to test validity of a pfn: > memblock_is_memory(pfn << PAGE_SHIFT); On LPAE systems this cuts off the top bits, as the shift occurs before the value is promoted to a phys_addr_t. This patch replaces the shift with a call to __pfn_to_phys (which casts pfn to phys_addr_t before shifting), preventing the loss of significant bits. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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